公开(公告)号：US07958290B2

公开(公告)日：2011-06-07

申请号：US10993702

申请日：2004-11-19

申请人： Jaishankar Thayyoor ,  Peter Martin

发明人： Jaishankar Thayyoor ,  Peter Martin

IPC分类号： G06F13/12 ,  G06F13/38

CPC分类号： G06F13/4291

摘要： The quantity of input and output signal lines that must be directly supported by a bus logic to transmit signals to and receive signals from bus devices is minimized by serializing the states to be driven onto the output signal lines and serially transmitting those states to one or more external shift registers having parallel outputs to drive output signal lines, by receiving states of input signal lines at parallel inputs to one or more other external shift registers to be serialized and serially transmitted to the bus logic, wherein the order in which the states to be driven onto the output signal lines is such that those states corresponding to actual output signal lines are the last states to be serially transmitted, and wherein the order in which the states received from the input signal lines are transmitted to the bus logic is such that those states corresponding to actual input signal lines are transmitted first to the bus logic, thereby also minimizing the quantity of shift registers required externally of the bus logic.

摘要翻译： 必须直接由总线逻辑支持的输入和输出信号线的数量通过串行化要驱动到输出信号线上的状态并将这些状态串行发送到一个或多个 外部移位寄存器具有并行输出以驱动输出信号线，通过将串行和串行发送到总线逻辑的一个或多个其它外部移位寄存器的并行输入的输入信号线的状态接收，其中状态为 驱动到输出信号线上的那些状态使得与实际输出信号线相对应的那些状态是要被串行发送的最后状态，并且其中从输入信号线接收到的状态被发送到总线逻辑的顺序使得那些 与实际输入信号线相对应的状态首先被发送到总线逻辑，从而也使偏移量r最小化 总线逻辑外部需要外部控制器。

公开(公告)号：US20060112202A1

公开(公告)日：2006-05-25

申请号：US10993702

申请日：2004-11-19

申请人： Jaishankar Thayyoor ,  Peter Martin

发明人： Jaishankar Thayyoor ,  Peter Martin

IPC分类号： G06F13/38

CPC分类号： G06F13/4291

摘要： The quantity of input and output signal lines that must be directly supported by a bus logic to transmit signals to and receive signals from bus devices is minimized by serializing the states to be driven onto the output signal lines and serially transmitting those states to one or more external shift registers having parallel outputs to drive output signal lines, by receiving states of input signal lines at parallel inputs to one or more other external shift registers to be serialized and serially transmitted to the bus logic, wherein the order in which the states to be driven onto the output signal lines is such that those states corresponding to actual output signal lines are the last states to be serially transmitted, and wherein the order in which the states received from the input signal lines are transmitted to the bus logic is such that those states corresponding to actual input signal lines are transmitted first to the bus logic, thereby also minimizing the quantity of shift registers required externally of the bus logic.

摘要翻译： 必须直接由总线逻辑支持的输入和输出信号线的数量通过串行化要驱动到输出信号线上的状态并将这些状态串行发送到一个或多个 外部移位寄存器具有并行输出以驱动输出信号线，通过将串行和串行发送到总线逻辑的一个或多个其它外部移位寄存器的并行输入的输入信号线的状态接收，其中状态为 驱动到输出信号线上的那些状态使得与实际输出信号线相对应的那些状态是要被串行发送的最后状态，并且其中从输入信号线接收到的状态被发送到总线逻辑的顺序使得那些 与实际输入信号线相对应的状态首先被发送到总线逻辑，从而也使偏移量r最小化 总线逻辑外部需要外部控制器。

公开(公告)号：US20050149657A1

公开(公告)日：2005-07-07

申请号：US10749076

申请日：2003-12-30

申请人： Peter Martin ,  Jaishankar Thayyoor

发明人： Peter Martin ,  Jaishankar Thayyoor

IPC分类号： G06F13/00 ,  G06F13/40

CPC分类号： G06F13/4081

摘要： According to embodiments of the present invention, a peripheral component interconnect (PCI) standard hot-plug controller (SHPC) includes a command register to store PCI slot operation commands for one or more target PCI slots and a programmable register that may be programmed with one timing parameter value (e.g., Tpccc, Tpece, Tcebe, Tbkrk, etc.) for a signal sequence for execution of one PCI slot operation command and another timing parameter value for a signal sequence for execution of another PCI slot operation command depending on the particular target PCI slot, the particular PCI slot operation command loaded into the command register, and/or the number of times a particular PCI slot operation command has been loaded into the command register, for example.

摘要翻译： 根据本发明的实施例，外围部件互连（PCI）标准热插拔控制器（SHPC）包括用于存储用于一个或多个目标PCI时隙的PCI时隙操作命令的命令寄存器和可以用一个 用于执行一个PCI插槽操作命令的信号序列的定时参数值（例如，Tpccc，Tpece，Tcebe，Tbkrk等）以及用于执行另一个PCI时隙操作命令的信号序列的另一定时参数值， 目标PCI插槽，加载到命令寄存器中的特定PCI插槽操作命令，和/或特定PCI插槽操作命令已被加载到命令寄存器中的次数。