公开(公告)号：US5040137A

公开(公告)日：1991-08-13

申请号：US449791

申请日：1989-12-13

申请人： James V. Sherrill

发明人： James V. Sherrill

IPC分类号： H03H17/06

CPC分类号： H03H17/06

摘要： A finite impulse response filter that has the ability to use arbitrary TAPs that are essentially random access TAPs includes a plurality of circuits. The samples it operates on do not need to be a contiguous form. A sequencer is provided for counting up to a programmable number each time a start pulse is encountered and to provide an address and an incrementing address to a delta RAM, a coefficient RAM, and a micro code RAM. The delta RAM is used for storing the number of the TAP that is to be accessed. Delta Adders that directly follow the delta RAM are used with an input counter for making a ring counter for the input samples. A first and second sample RAM are used to hold incoming samples. An adder circuit is used for adding the output of the two sample RAMs to provide an output signal. A multiplier accumulator is connected to the adder circuit for receiving the output signal. The sequencer provides all the timing for the different cycles of the multiplier accumulator. After a programmed amount of samples have been added together, the multiplier accumulator outputs its value onto an input/output bus, where all the input and output samples either originate or end.

摘要翻译： 具有使用基本随机接入TAP的任意TAP的能力的有限脉冲响应滤波器包括多个电路。 其操作的样品不需要是连续的形式。 提供了一个定序器，用于在每次遇到起始脉冲时对多达可编程数进行计数，并向delta RAM，系数RAM和微代码RAM提供地址和递增地址。 增量RAM用于存储要访问的TAP的数量。 直接跟随增量RAM的Delta Adders与输入计数器一起使用，用于为输入采样设置振铃计数器。 第一和第二采样RAM用于保存传入的采样。 加法器电路用于将两个采样RAM的输出相加以提供输出信号。 乘法器累加器连接到加法器电路以接收输出信号。 定序器为乘法器累加器的不同周期提供所有时序。 在编程的样本数量加在一起之后，乘法器累加器将其值输出到输入/输出总线上，其中所有的输入和输出样本均起始或结束。

公开(公告)号：US4821208A

公开(公告)日：1989-04-11

申请号：US918305

申请日：1986-10-14

申请人： Lawrence D. Ryan ,  James V. Sherrill ,  Robert D. Shedd ,  Gerald T. Caracciolo

发明人： Lawrence D. Ryan ,  James V. Sherrill ,  Robert D. Shedd ,  Gerald T. Caracciolo

IPC分类号： G09G5/06 ,  G06F3/153 ,  G09G1/28

CPC分类号： G09G5/06

摘要： A display processor, as for a small computer, processes pixel codes of various lengths. Three addressable color maps have their read addresses generated independently from portions of each pixel code. The portions of each pixel code used in generating each read address can be selected by programming.

摘要翻译： 对于小型计算机，显示处理器处理各种长度的像素码。 三个可寻址的颜色图具有独立于每个像素代码的部分生成的读地址。 可以通过编程来选择用于生成每个读取地址的每个像素码的部分。

公开(公告)号：US4791580A

公开(公告)日：1988-12-13

申请号：US918552

申请日：1986-10-14

申请人： James V. Sherrill ,  David L. Sprague

发明人： James V. Sherrill ,  David L. Sprague

IPC分类号： G09G5/06 ,  G09G1/16

CPC分类号： G09G5/06

摘要： A display processor for a computer with graphics capability includes color map memories addressed by portions of pixel codes during display line trace intervals. The read-outs from these color map memories provide the primary color component signals from which the drive signals for the display monitor kinescope are derived. The pixel codes, from which color map memory addresses are derived, are supplied at video rate to the display processor from the serial output port of dual-ported video random access memory. The color map memories are loaded with new color map data during display retrace intervals. By supplying this new color map data from the serial port of the dual-ported video random-access memory, the color map memories can be rapidly updated.

摘要翻译： 用于具有图形能力的计算机的显示处理器包括在显示行跟踪间隔期间由像素代码的部分寻址的彩色映射存储器。 从这些彩色映射存储器的读出提供了用于显示显示器显像管的驱动信号得到的原色分量信号。 从双端口视频随机存取存储器的串行输出端口以视频速率向显示处理器提供从其导出颜色映射存储器地址的像素码。 在显示回扫间隔期间，颜色映射存储器加载新的颜色映射数据。 通过从双端口视频随机存取存储器的串行端口提供这种新的颜色映射数据，可以快速更新颜色映射存储器。