公开(公告)号：US4744095A

公开(公告)日：1988-05-10

申请号：US895528

申请日：1986-08-11

Applicant: Jean-Francois R. Cornet ,  Patrick Clement

Inventor： Jean-Francois R. Cornet ,  Patrick Clement

IPC: H04B1/74 ,  H04L1/02 ,  H04L7/00

CPC classification number: H04L1/02

Abstract: An arrangement ensuring the change-over of two channels through which the same digital information is conveyed with automatic data alignment over a .+-.3.5 bit range comprises for each channel an array of buffer stores operating at a write rate H.sub.i /N.sub.i (where i=1, 2), an oscillator operating at a rate H which provides reading of the buffer stores at the rate H/N and being synchronized in phase-opposition with one or the other of the write rates, and a logic comparator controlling the write rates H.sub.i /N.sub.i, the routing of the write rates to the input of the oscillator, as well as a change-over switch for the data.In the buffer store of the channel assumed to be the one whose quality degrades, the data are converted into N parallel streams at the rate H.sub.2 /N and are read at the rate H/N of the oscillator. In the other channel, the write rate of the buffer store is forced to the rate H.sub.1 /N-1, the read rate remaining unchanged, until there is a coincidence of N bits in the two channels; thereupon the data stream is switched, the write rate is locked at H.sub.1 /N and this write rate is applied to the oscillator.

Abstract translation: 确保在+/- 3.5位范围内自动数据对齐传送相同数字信息的两个通道的切换的布置包括：对于每个通道，以写入速率Hi / Ni（其中i = 1,2），以以速率H / N提供对缓冲器的读取的速率H操作的振荡器，并且与写入速率中的一个或另一个以相位对准的方式同步;以及控制写入的逻辑比较器 速率Hi / Ni，写入速率到振荡器的输入的路由，以及数据的切换开关。 在假定为质量劣化的信道的缓冲存储器中，将数据以速率H2 / N转换成N个并行流，并以振荡器的速率H / N读取。 在另一个通道中，缓冲存储器的写入速率被强制为速率H1 / N-1，读取速率保持不变，直到两个通道中存在N位一致; 随后数据流被切换，写入速率被锁定在H1 / N，并且该写入速率被施加到振荡器。