公开(公告)号：US07707266B2

公开(公告)日：2010-04-27

申请号：US10997624

申请日：2004-11-23

申请人： Sridhar Lakshmanamurthy ,  Mark B. Rosenbluth ,  Matthew Adiletta ,  Jeen-Xuan Miin ,  Bijoy Bose

发明人： Sridhar Lakshmanamurthy ,  Mark B. Rosenbluth ,  Matthew Adiletta ,  Jeen-Xuan Miin ,  Bijoy Bose

IPC分类号： G06F13/00 ,  G06F15/173 ,  G06F15/16

CPC分类号： G06F15/7842 ,  G06F15/8007

摘要： A scalable, high-performance interconnect scheme for a multi-threaded, multi-processing system-on-a-chip network processor unit. An apparatus implementing the technique includes a plurality of masters configured in a plurality of clusters, a plurality of targets, and a chassis interconnect that may be controlled to selectively connects a given master to a given target. In one embodiment, the chassis interconnect comprises a plurality of sets of bus lines connected between the plurality of clusters and the plurality of targets forming a cross-bar interconnect, including sets of bus lines corresponding to a command bus, a pull data bus for target writes, and a push data bus for target reads. Multiplexer circuitry for each of the command bus, pull data bus, and push data bus is employed to selectively connect a given cluster to a given target to enable commands and data to be passed between the given cluster and the given target.

摘要翻译： 用于多线程，多处理片上系统处理器单元的可扩展的高性能互连方案。 实现该技术的装置包括配置在多个集群中的多个主机，多个目标以及可被控制以选择性地将给定主机连接到给定目标的机箱互连。 在一个实施例中，机箱互连包括连接在多个群集之间的多组总线，并且多个目标形成横杆互连，包括对应于命令总线的总线线路，用于目标的拉动数据总线 写入和用于目标读取的推送数据总线。 采用用于每个命令总线，拉数据总线和推数据总线的多路复用器电路来选择性地将给定集群连接到给定目标，以使命令和数据能够在给定集群和给定目标之间传递。