公开(公告)号：US5506814A

公开(公告)日：1996-04-09

申请号：US69967

申请日：1993-05-28

申请人： Glen Hush ,  Mike Seibert ,  Jeff Mailloux ,  Mark R. Thomann

发明人： Glen Hush ,  Mike Seibert ,  Jeff Mailloux ,  Mark R. Thomann

IPC分类号： G11C7/10 ,  G11C8/00

CPC分类号： G11C7/1006 ,  G11C7/1033 ,  G11C7/1075

摘要： The invention is a monolithic video random access memory (VRAM) chip that has more than one write control pin which is used to segment the VRAM into banks or sub-chips having four DQ planes such that a nibble of data can be written to the VRAM. Using the method of the invention a first bank may be written independently of a second bank, such that during a single memory cycle the first bank may be written and the second bank may be read. The VRAM of the invention functions without the masking of a write to either bank. In addition the write memory function can be performed either through the random access memory port or through the serial access memory port.

摘要翻译： 本发明是具有多于一个写入控制引脚的单片视频随机存取存储器（VRAM）芯片，其用于将VRAM分割成具有四个DQ平面的存储体或子芯片，使得可以将数据的半字节写入VRAM 。 使用本发明的方法，可以独立于第二组来写入第一存储体，使得在单个存储器周期期间可以写入第一存储体并且可以读取第二存储体。 本发明的VRAM在不掩蔽任何一个存储体的写入的情况下起作用。 此外，写入存储器功能可以通过随机存取存储器端口或通过串行存取存储器端口执行。

公开(公告)号：US5703826A

公开(公告)日：1997-12-30

申请号：US619285

申请日：1996-03-18

申请人： Glen Hush ,  Mike Seibert ,  Jeff Mailloux ,  Mark R. Thomann

发明人： Glen Hush ,  Mike Seibert ,  Jeff Mailloux ,  Mark R. Thomann

IPC分类号： G11C7/10 ,  G11C8/00

CPC分类号： G11C7/1006 ,  G11C7/1033 ,  G11C7/1075

摘要： The invention is a monolithic video random access memory (VRAM) chip that has more than one write control pin which is used to segment the VRAM into banks or sub-chips having four DQ planes such that a nibble of data can be written to the VRAM. Using the method of the invention a first bank may be written independently of a second bank, such that during a single memory cycle the first bank may be written and the second bank may be read. Using the circuit of the invention data is transferred in response to an internal write signal. The VRAM of the invention functions without the masking of a write to either bank. In addition the write memory function can be performed either through the random access memory port or through the serial access memory port.

摘要翻译： 本发明是具有多于一个写入控制引脚的单片视频随机存取存储器（VRAM）芯片，其用于将VRAM分割成具有四个DQ平面的存储体或子芯片，使得可将数据的半字节写入VRAM 。 使用本发明的方法，可以独立于第二组来写入第一存储体，使得在单个存储器周期期间可以写入第一存储体并且可以读取第二存储体。 使用本发明的电路响应于内部写入信号传送数据。 本发明的VRAM在不掩蔽任何一个存储体的写入的情况下起作用。 此外，写入存储器功能可以通过随机存取存储器端口或通过串行存取存储器端口执行。

公开(公告)号：US5699314A

公开(公告)日：1997-12-16

申请号：US732943

申请日：1996-10-17

申请人： Glen Hush ,  Mike Seibert ,  Jeff Mailloux ,  Mark R. Thomann

发明人： Glen Hush ,  Mike Seibert ,  Jeff Mailloux ,  Mark R. Thomann

IPC分类号： G11C7/10 ,  G11C8/00

CPC分类号： G11C7/1006 ,  G11C7/1033 ,  G11C7/1075

摘要： The invention is a monolithic video random access memory (VRAM) chip that has more than one write control pin which is used to segment the VRAM into banks or sub-chips having four DQ planes such that a nibble of data can be written to the VRAM. Using the method of the invention a first bank may be written independently of a second bank, such that during a single memory cycle the first bank may be written and the second bank may be read. The VRAM of the invention functions without the masking of a write to either bank. In addition the write memory function can be performed either through the random access memory port or through the serial access memory port.

摘要翻译： 本发明是具有多于一个写入控制引脚的单片视频随机存取存储器（VRAM）芯片，其用于将VRAM分割成具有四个DQ平面的存储体或子芯片，使得可以将数据的半字节写入VRAM 。 使用本发明的方法，可以独立于第二组来写入第一存储体，使得在单个存储器周期期间可以写入第一存储体并且可以读取第二存储体。 本发明的VRAM在不掩蔽任何一个存储体的写入的情况下起作用。 此外，写入存储器功能可以通过随机存取存储器端口或通过串行存取存储器端口执行。