公开(公告)号：US20130179662A1

公开(公告)日：2013-07-11

申请号：US13348544

申请日：2012-01-11

Applicant: Jack CHOQUETTE ,  Xiaogang Qiu ,  Jeff Tuckey ,  Michael (Ming Yiu) Siu ,  Robert J. Stoll ,  Olivier Giroux

Inventor： Jack CHOQUETTE ,  Xiaogang Qiu ,  Jeff Tuckey ,  Michael (Ming Yiu) Siu ,  Robert J. Stoll ,  Olivier Giroux

IPC: G06F9/30 ,  G06F9/312 ,  G06F9/38

CPC classification number: G06F9/3887 ,  G06F9/3851

Abstract: An address divergence unit detects divergence between threads in a thread group and then separates those threads into a subset of non-divergent threads and a subset of divergent threads. In one embodiment, the address divergence unit causes instructions associated with the subset of non-divergent threads to be issued for execution on a parallel processing unit, while causing the instructions associated with the subset of divergent threads to be re-fetched and re-issued for execution.

Abstract translation: 地址发散单元检测线程组中的线程之间的差异，然后将这些线程分成非发散线程的子集和发散线程的子集。 在一个实施例中，地址发散单元导致与非发散线程的子集相关联的指令用于在并行处理单元上执行，同时引起与分支线程的子集相关联的指令被重新获取并重新发布 执行。

公开(公告)号：US06591316B1

公开(公告)日：2003-07-08

申请号：US09315275

申请日：1999-05-20

Applicant: Peter Roman ,  Jeff Tuckey ,  Parthiban Kandappan

Inventor： Peter Roman ,  Jeff Tuckey ,  Parthiban Kandappan

IPC: G06F300

CPC classification number: H04L29/06 ,  H04L49/90

Abstract: A packet memory interface. The interface includes an input mechanism which receives related data. The interface includes an output mechanism which transmits the data. The interface includes a mechanism for transferring at least a plurality of bytes of the data in each burst of a plurality of bursts from the input mechanism to the output mechanism without fragmentation loss in each burst. A method for transferring data through a packet memory interface. The method includes the steps of receiving data of the packet at an input mechanism of the interface. Then there is the step of transferring at least a plurality of bytes of data of the packet to an output mechanism in bursts without any fragmentation loss in the bursts.

Abstract translation: 分组存储器接口。 该接口包括接收相关数据的输入机构。 该接口包括发送数据的输出机构。 该接口包括用于将多个突发的每个突发中的数据的至少多个字节的数据从输入机制传送到输出机制的机制，而不会在每个突发中产生分段损失。 一种通过数据包存储器接口传输数据的方法。 该方法包括以下步骤：在接口的输入机制处接收数据包的数据。 然后，将脉冲串中的分组的至少多个字节的数据传送到输出机制，并且在脉冲串中没有任何分段丢失的步骤。

公开(公告)号：US09606808B2

公开(公告)日：2017-03-28

申请号：US13348544

申请日：2012-01-11

Applicant: Jack Choquette ,  Xiaogang Qiu ,  Jeff Tuckey ,  Michael (Ming Yiu) Siu ,  Robert J. Stoll ,  Olivier Giroux

Inventor： Jack Choquette ,  Xiaogang Qiu ,  Jeff Tuckey ,  Michael (Ming Yiu) Siu ,  Robert J. Stoll ,  Olivier Giroux

IPC: G06F9/38

CPC classification number: G06F9/3887 ,  G06F9/3851

Abstract: A computing device detects divergences between threads in a thread group executing on a parallel processing unit. The computing device includes an address divergence unit that identifies a subset of non-divergent threads included in the thread group. The address divergence unit stores instructions related to the subset of non-divergent threads in a multi-issue queue. The address divergence unit causes the instructions related to the subset of non-divergent threads to be retrieved from the multi-issue queue when the parallel processing unit is available. The address divergence unit causes the subset of non-divergent threads to be issued for execution on the parallel processing unit. The address divergence unit repeats the identifying, storing, and causing steps for the remaining threads in the thread group that are not included in the subset of non-divergent threads.