公开(公告)号：US20050215024A1

公开(公告)日：2005-09-29

申请号：US11069501

申请日：2005-03-01

申请人： Jeong-Yeop Nahm ,  Helmut Puchner ,  Oliver Pohland ,  Yangzhong Xu

发明人： Jeong-Yeop Nahm ,  Helmut Puchner ,  Oliver Pohland ,  Yangzhong Xu

IPC分类号： H01L21/336 ,  H01L21/76 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/739 ,  H01L29/78

CPC分类号： H01L29/1045 ,  H01L21/823814 ,  H01L29/1083 ,  H01L29/66492 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

摘要： Methods for fabricating diffusion regions having steep concentration profiles within MOS devices while minimizing junction capacitance degradation are provided. In particular, methods are provided which include patterning a gate structure upon a semiconductor substrate and subsequently etching a recess in exposed portions of the substrate. In some cases, the method includes forming a first dopant region within the exposed portions prior to etching the recess. The method may additionally or alternatively include implanting a second set of dopants into portions of the semiconductor substrate bordering the recess. In either case, the method includes growing an epitaxial layer within the recess and implanting a third set of dopants into the semiconductor topography to form a second dopant region extending to a depth at least within the epitaxial layer. A resulting semiconductor topography includes a source/drain region comprising an upper portion consisting essentially of first dopants of a first conductivity type.

摘要翻译： 提供了在MOS器件内制造具有陡峭浓度分布的扩散区，同时最小化结电容劣化的方法。 特别地，提供了包括在半导体衬底上图案化栅极结构并随后蚀刻衬底的暴露部分中的凹部的方法。 在一些情况下，该方法包括在蚀刻凹槽之前在暴露部分内形成第一掺杂区域。 该方法可以附加地或替代地包括将第二组掺杂剂注入到与凹部接合的半导体衬底的部分中。 在任一情况下，该方法包括在凹槽内生长外延层并将第三组掺杂剂注入到半导体形貌中以形成延伸至至少在外延层内的深度的第二掺杂区。 得到的半导体形貌包括源/漏区，其包括基本上由第一导电类型的第一掺杂剂组成的上部。

公开(公告)号：US07105413B2

公开(公告)日：2006-09-12

申请号：US11069501

申请日：2005-03-01

申请人： Jeong-Yeop Nahm ,  Helmut Puchner ,  Oliver Pohland ,  Yangzhong Xu

发明人： Jeong-Yeop Nahm ,  Helmut Puchner ,  Oliver Pohland ,  Yangzhong Xu

IPC分类号： H01L21/336

CPC分类号： H01L29/1045 ,  H01L21/823814 ,  H01L29/1083 ,  H01L29/66492 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

摘要： Methods for fabricating diffusion regions having steep concentration profiles within MOS devices while minimizing junction capacitance degradation are provided. In particular, methods are provided which include patterning a gate structure upon a semiconductor substrate and subsequently etching a recess in exposed portions of the substrate. In some cases, the method includes forming a first dopant region within the exposed portions prior to etching the recess. The method may additionally or alternatively include implanting a second set of dopants into portions of the semiconductor substrate bordering the recess. In either case, the method includes growing an epitaxial layer within the recess and implanting a third set of dopants into the semiconductor topography to form a second dopant region extending to a depth at least within the epitaxial layer. A resulting semiconductor topography includes a source/drain region comprising an upper portion consisting essentially of first dopants of a first conductivity type.

摘要翻译： 提供了在MOS器件内制造具有陡峭浓度分布的扩散区，同时最小化结电容劣化的方法。 特别地，提供了包括在半导体衬底上图案化栅极结构并随后蚀刻衬底的暴露部分中的凹部的方法。 在一些情况下，该方法包括在蚀刻凹槽之前在暴露部分内形成第一掺杂区域。 该方法可以附加地或替代地包括将第二组掺杂剂注入到与凹部接合的半导体衬底的部分中。 在任一情况下，该方法包括在凹槽内生长外延层并将第三组掺杂剂注入到半导体形貌中以形成延伸至至少在外延层内的深度的第二掺杂区。 得到的半导体形貌包括源/漏区，其包括基本上由第一导电类型的第一掺杂剂组成的上部。