公开(公告)号：US20080250376A1

公开(公告)日：2008-10-09

申请号：US11732848

申请日：2007-04-04

申请人： Jerry R. Burch ,  Robert F. Damiano ,  Pei-Hsin Ho ,  James H. Kukula

发明人： Jerry R. Burch ,  Robert F. Damiano ,  Pei-Hsin Ho ,  James H. Kukula

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  G06F17/504

摘要： One embodiment of the present invention provides a system that routes a set of pairs of points during the design of an integrated circuit (IC) chip. The system comprises a routing engine which is configured to search for a path to connect a current pair of points in the set of pairs of points, wherein the path comprises a set of rectangles and vertices. The routing engine uses a routing database, which keeps track of previously routed nets that can obstruct the routing of the current pair of points. The system further comprises a satisfiability (SAT) solver which is capable of solving a set of constraints, wherein the set of constraints are associated with the routability of the set of pairs of points. The SAT solver additionally comprises a SAT database which maintains the set of constraints and a current partial solution to the set of constraints. The SAT database is used to update the routing database if the current partial solution changes.

摘要翻译： 本发明的一个实施例提供了一种在集成电路（IC）芯片的设计期间路由一组点对的系统。 该系统包括路由引擎，其被配置为搜索路径以连接该组对点中的当前点对，其中该路径包括一组矩形和顶点。 路由引擎使用路由数据库，其跟踪可阻碍当前对点对的路由的先前路由网络。 该系统还包括能够求解一组约束的可满足性（SAT）求解器，其中所述约束集合与所述一组点对的可路由性相关联。 SAT求解器还包括一个SAT数据库，该数据库维护一组约束，并且对该组约束的当前部分解决方案。 如果当前部分解决方案发生变化，SAT数据库将用于更新路由数据库。

公开(公告)号：US07904867B2

公开(公告)日：2011-03-08

申请号：US11732848

申请日：2007-04-04

申请人： Jerry R. Burch ,  Robert F. Damiano ,  Pei-Hsin Ho ,  James H. Kukula

发明人： Jerry R. Burch ,  Robert F. Damiano ,  Pei-Hsin Ho ,  James H. Kukula

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  G06F17/504

摘要： One embodiment of the present invention provides a system that routes a set of pairs of points during the design of an integrated circuit (IC) chip. The system comprises a routing engine which is configured to search for a path to connect a current pair of points in the set of pairs of points, wherein the path comprises a set of rectangles and vertices. The routing engine uses a routing database, which keeps track of previously routed nets that can obstruct the routing of the current pair of points. The system further comprises a satisfiability (SAT) solver which is capable of solving a set of constraints, wherein the set of constraints are associated with the routability of the set of pairs of points. The SAT solver additionally comprises a SAT database which maintains the set of constraints and a current partial solution to the set of constraints. The SAT database is used to update the routing database if the current partial solution changes.

摘要翻译： 本发明的一个实施例提供了一种在集成电路（IC）芯片的设计期间路由一组点对的系统。 该系统包括路由引擎，其被配置为搜索路径以连接该组对点中的当前点对，其中该路径包括一组矩形和顶点。 路由引擎使用路由数据库，其跟踪可阻碍当前对点对的路由的先前路由网络。 该系统还包括能够求解一组约束的可满足性（SAT）求解器，其中所述约束集合与所述一组点对的可路由性相关联。 SAT求解器还包括一个SAT数据库，该数据库维护一组约束，并且对该组约束的当前部分解决方案。 如果当前部分解决方案发生变化，SAT数据库将用于更新路由数据库。

公开(公告)号：US06308299B1

公开(公告)日：2001-10-23

申请号：US09118199

申请日：1998-07-17

申请人： Jerry R. Burch ,  Vigyan Singhal

发明人： Jerry R. Burch ,  Vigyan Singhal

IPC分类号： G06F1750

CPC分类号： G06F17/504

摘要： A method and system for combinational verification tightly integrates multiple verification methods. The present invention performs random simulation on the inputs of two combinational netlists. The nets within the netlists are described as BDDs and divided into classes of cutpoint candidates based upon the signatures produced by the random simulation. Cutpoint candidates within each class are resolved to determine whether the candidates are equivalent. If the nets are likely to be equivalent, BDD composition is performed on the nets. Otherwise, SAT-based analysis is performed on the nets. If either method fails to resolve the cutpoints within an allocated amount of time or resources, then the other method is invoked and information learned by the first method is passed to the second method to assist in the resolution. This process repeats until the cutpoint candidates are resolved. If the cutpoint resolution produces a true negative, then the candidate classes are refined by performing directed simulation on the inputs of the netlists using the witness to the true negative generated by the cutpoint resolution. This directed simulation produces new candidate classes that are resolved as described above. If, after the cutpoint classes are refined, the outputs are in a different class, then the netlists are unequal. If a false negative is found after the cutpoints are resolved, a new cutpoint is created. If the outputs are in the current class, then the two netlists are equal. Otherwise, the cutpoints are further resolved as described above.

摘要翻译： 组合验证的方法和系统将多种验证方法相结合。 本发明对两个组合网表的输入进行随机模拟。 网表中的网络被描述为BDD，并且基于随机模拟产生的签名被划分成等级的候选点。 解决每个类别中的切入点候选人，以确定候选人是否等同。 如果网络可能相当，BDD组合就在网络上执行。 否则，在网络上执行基于SAT的分析。 如果任一方法无法在分配的时间或资源中解析切点，则调用另一种方法，并将第一种方法学习的信息传递给第二种方法以协助解析。 这个过程重复，直到临界点被解决。 如果切点分辨率产生真正的负数，则通过使用对切分点分辨率产生的真实负数的证人对网表的输入执行定向模拟来改进候选类。 该定向仿真产生如上所述解析的新候选类。 如果在精简分类后，输出处于不同的类，那么网表不平等。 如果在切割点解决后发现假阴性，则会创建一个新的切点。 如果输出在当前类中，则两个网表相等。 否则，如上所述进一步解析切点。

公开(公告)号：US06247163B1

公开(公告)日：2001-06-12

申请号：US09172708

申请日：1998-10-13

申请人： Jerry R. Burch ,  Vigyan Singhal

发明人： Jerry R. Burch ,  Vigyan Singhal

IPC分类号： G06F1560

CPC分类号： G06F17/504

摘要： A method and system of latch mapping for performing combinational equivalence checking on a specification and an implementation of a circuit that does not depend on signal names or circuit structure to determine the latch mapping. First, every latch is mapped to every other latch. Then, the resulting mapping is refined until it is semi-inductive. The refinement is performed by randomly producing a state that satisfies the mapping and applying a random input vector to the circuits. The resulting mappings are iteratively compared and new input vectors are applied to the circuits until the greatest fixed point of the refinement is found. Then, it is determined whether the greatest fixed point of refinement forces output equality. If the greatest fixed point does not force output equality, then a bug in a combinational block of the implementation is localized through an interactive procedure. If the greatest fixed point does force output equality, then it is determined whether it also satisfies a reset condition. If implementation latches are not mapped together, then conformance with the reset condition is guaranteed. Otherwise, conformance can be guaranteed only if the implementation latches mapped together are assumed to have the same value in the reset state. The method and system is also extended to cover ternary latch mappings having “don't care” conditions.

摘要翻译： 一种锁存映射的方法和系统，用于对不依赖于信号名称或电路结构的电路的规范和实现进行组合等价检查，以确定锁存器映射。 首先，每个锁存器映射到每隔一个锁存器。 然后，所得到的映射被改进，直到它是半归纳。 通过随机产生满足映射并将随机输入向量应用于电路的状态来进行细化。 迭代地比较所得到的映射，并且将新的输入向量应用于电路，直到发现细化的最大定点。 然后，确定最大固定点的精确力是否输出相等。 如果最大的固定点不强制输出相等，那么实现的组合块中的错误通过交互式过程进行本地化。 如果最大的固定点强制输出相等，则确定它是否也满足复位条件。 如果实现锁存器未映射到一起，则保证符合复位条件。 否则，只有在映射到一起的实现锁存器在复位状态下被假定为具有相同的值时，才能保证一致性。 该方法和系统也被扩展到覆盖具有“无关紧要”条件的三进制锁存器映射。