公开(公告)号：US07370310B1

公开(公告)日：2008-05-06

申请号：US11200454

申请日：2005-08-08

Applicant: Milan R. Saini ,  Jibin Han

Inventor： Milan R. Saini ,  Jibin Han

IPC: G06F17/50 ,  H03K17/693

CPC classification number: G06F17/5054

Abstract: Address map generation is described. More particularly, static addresses are obtained. A system design at least a portion of which is for instantiation in configurable logic of an integrated circuit is obtained. The system design includes a processor. At least one predefined circuit block in the design is identified as a peripheral connected to a processor. The at least one predefined circuit block is for instantiation in the configurable logic of the integrated circuit. Assigned to the at least one predefined circuit block is a static address range which is obtained from the static addresses. An address map for the design is generated having the at least one predefined circuit block with the static address range. Thus, for example, independent designers designing separate systems having a same set of peripherals may map to the same static address ranges independent of software system builder tool version, board, or processor used.

Abstract translation: 描述地址映射生成。 更具体地，获得静态地址。 获得其集成电路的可配置逻辑中的至少一部分用于实例化的系统设计。 系统设计包括一个处理器。 设计中至少一个预定义的电路块被识别为连接到处理器的外设。 至少一个预定义的电路块用于在集成电路的可配置逻辑中实例化。 分配给至少一个预定义的电路块是从静态地址获得的静态地址范围。 产生用于设计的地址图，其具有至少一个具有静态地址范围的预定义的电路块。 因此，例如，独立设计者设计具有相同外设的单独系统可以映射到独立于所使用的软件系统构建器工具版本，板或处理器的相同的静态地址范围。

公开(公告)号：US08359557B1

公开(公告)日：2013-01-22

申请号：US13100013

申请日：2011-05-03

Applicant: Xi Chen ,  Jibin Han ,  Paulo L. Dutra ,  Thien Than ,  Biping Wu

Inventor： Xi Chen ,  Jibin Han ,  Paulo L. Dutra ,  Thien Than ,  Biping Wu

IPC: G06F17/50

CPC classification number: G06F17/505

Abstract: A method is provided for generation of a circuit design. A plurality of components, including at least a processor and a peripheral device, is instantiated in a circuit design. One or more parameterizable data bus interface blocks are automatically selected based on the master-slave relationships, requirements, and capabilities of the components. The one or more parameterizable data bus interface blocks are instantiated in the circuit design. In response to user input, values are assigned to one or more parameters of the processor. The plurality of components and data bus interface blocks are automatically parameterized by determining appropriate parameter values according to the parameters of the processor and capabilities and requirements of the components and data bus interface blocks.

Abstract translation: 提供了一种用于产生电路设计的方法。 包括至少处理器和外围设备的多个组件在电路设计中被实例化。 基于组件的主 - 从关系，要求和功能自动选择一个或多个可参数化的数据总线接口块。 一个或多个可参数化的数据总线接口块在电路设计中被实例化。 响应于用户输入，值被分配给处理器的一个或多个参数。 通过根据处理器的参数和组件和数据总线接口块的能力和要求确定适当的参数值来自动地对多个组件和数据总线接口块进行参数化。