公开(公告)号：US4896266A

公开(公告)日：1990-01-23

申请号：US57460

申请日：1987-06-03

Applicant: John A. Klashka ,  Sidney L. Kaufman ,  Krzysztof A. Kowal ,  Richard P. Lewis ,  John L. McNamara, Jr.

Inventor： John A. Klashka ,  Sidney L. Kaufman ,  Krzysztof A. Kowal ,  Richard P. Lewis ,  John L. McNamara, Jr.

IPC: G06F13/28 ,  G06F13/37

CPC classification number: G06F13/28 ,  G06F13/37

Abstract: The present invention relates to a computer system having a sequence controller for allowing direct memory access devices to access peripheral devices. The sequence controller allows the peripheral devices access to a global bus by providing access in a round-robin fashion. A microprocessor associated with the sequence controller and direct memory access has access to the global bus after each direct memory access. The amount of data allowed to be transferred in each direct memory access is restricted so that each device is equally serviced.

Abstract translation: 本发明涉及具有用于允许直接存储器访问设备访问外围设备的顺序控制器的计算机系统。 序列控制器允许外围设备通过以循环方式提供访问来访问全局总线。 与序列控制器和直接存储器访问相关联的微处理器在每次直接存储器访问之后都可访问全局总线。 在每个直接存储器访问中允许传送的数据量受到限制，以使每个设备得到同样的服务。

公开(公告)号：US4803623A

公开(公告)日：1989-02-07

申请号：US925431

申请日：1986-10-31

Applicant: John A. Klashka ,  Sidney L. Kaufman ,  Krzysztof A. Kowal ,  Richard P. Lewis ,  Susan L. Raisbeck ,  John L. McNamara, Jr.

Inventor： John A. Klashka ,  Sidney L. Kaufman ,  Krzysztof A. Kowal ,  Richard P. Lewis ,  Susan L. Raisbeck ,  John L. McNamara, Jr.

IPC: G06F13/38 ,  G06F15/177 ,  G06F13/10

CPC classification number: G06F15/177 ,  G06F13/385

Abstract: In a computer system having at least a bus with at least one central processing unit (CPU), one random access memory (RAM), and a first configuration of a plurality of different types of peripheral units (e.g. tape drives, disk drives, diskette drives, printers, unit record peripherals, etc.) coupled to the bus, an apparatus for controlling the first configuration and also capable of controlling a predetermined number of other configurations of different types of peripheral units when any of that predetermined number of configurations of peripheral units is coupled to the bus.

公开(公告)号：US5155810A

公开(公告)日：1992-10-13

申请号：US295683

申请日：1989-01-10

Applicant: John L. McNamara, Jr. ,  Donald J. Rathbun

Inventor： John L. McNamara, Jr. ,  Donald J. Rathbun

IPC: G06F13/12

CPC classification number: G06F13/122

Abstract: An adapter is connected between a peripheral controller and an intelligent peripheral device. The adapter allows the peripheral device to communicate with the controller. The adapter has control logic rather than a microprocessor for transmitting and receiving data. The control logic is comprised of combinatorial logic circuitry and a command register. The command register allows the controller to configure the cominatorial logic circuitry in order to control adapter operation.

Abstract translation: 外部控制器和智能外围设备之间连接有一个适配器。 适配器允许外围设备与控制器通信。 适配器具有控制逻辑，而不是用于发送和接收数据的微处理器。 控制逻辑由组合逻辑电路和命令寄存器组成。 命令寄存器允许控制器配置组合逻辑电路，以控制适配器的操作。