公开(公告)号：US06298105B1

公开(公告)日：2001-10-02

申请号：US09183031

申请日：1998-10-30

申请人： Xia Dai ,  George Geannopuolos ,  John Orton ,  Keng Wong ,  Greg F. Taylor

发明人： Xia Dai ,  George Geannopuolos ,  John Orton ,  Keng Wong ,  Greg F. Taylor

IPC分类号： H04L100

CPC分类号： G06F1/3287 ,  G06F1/10 ,  G06F1/3203 ,  H03L7/0814 ,  H03L7/087 ,  Y02D10/171

摘要： An apparatus for a low skew, low standby power clock network for a synchronous digital system. The power clock network comprises a reference network, maintaining a reference clock signal, and four clock spines, each with its own respective clock signal. To reduce clock skew within the power clock network (i.e., to keep the clock signals of the clock spines synchronous with the reference clock signal), the present invention employs the use of active and passive delay elements to compensate for such skew. A phase relation extraction logic compares the phase of the clock signals from each respective clock spine to the reference clock signal of the reference network. If it is determined that the clock signals of the spines lag the reference clock signal, the phase relation extraction logic will use an active control driver to “speed-up” the clock signals of the clock spines. And, if the clock signals of the clock spines lead the reference clock signal, the phase relation extraction logic will use capacitive loadings to “slow down” such clock signals. Advantageously, the likelihood of the microprocessor achieving its maximum operating potential is greatly enhanced by the synchronization of such signals.

摘要翻译： 一种用于同步数字系统的低偏移，低待机功率时钟网络的装置。 功率时钟网络包括参考网络，维护参考时钟信号和四个时钟棘轮，每个具有其各自的时钟信号。 为了减少功率时钟网络内的时钟偏移（即，使时钟的时钟信号与参考时钟信号保持同步），本发明采用有源和无源延迟元件来补偿这种偏移。 相位关系提取逻辑将来自每个相应时钟脊的时钟信号的相位与参考网络的参考时钟信号进行比较。 如果确定脊柱的时钟信号滞后于参考时钟信号，则相位关系提取逻辑将使用主动控制驱动器来“加速”时钟棘轮的时钟信号。 而且，如果时钟的时钟信号引导参考时钟信号，则相位关系提取逻辑将使用电容负载来“减慢”这样的时钟信号。 有利地，通过这种信号的同步，微处理器实现其最大工作电位的可能性大大提高。