公开(公告)号：US06185450B2

公开(公告)日：2001-02-06

申请号：US09013570

申请日：1998-01-26

申请人： Dennis R. Seguine ,  John R. Stice ,  Stephen P. LaBrash

发明人： Dennis R. Seguine ,  John R. Stice ,  Stephen P. LaBrash

IPC分类号： A61B50428

CPC分类号： A61B5/0428 ,  Y10S128/901

摘要： A method and apparatus for monitoring an electrocardiograph waveform, and for returning an electrocardiograph trace to the middle of a display, such as a chart recorder strip. The monitoring circuit includes an amplifier and a switch for switching the frequency response curve of the monitoring circuit. In a first position, the switch causes the monitoring circuit to have a slow frequency response curve, which allows for accurate monitoring of ECG waveforms. In a second position, the switch causes the monitoring circuit to have a fast frequency response curve, which allows the amplifier of the monitoring circuit to quickly be brought out of saturation. The amplifier of the monitoring circuit becomes saturated when a defibrillation or pace pulse has been applied to a patient who is being monitored. The switch is controlled by a pulse waveform control signal that is provided by a microprocessor. By varying the duty cycle of the control signal, the frequency response curve of the monitoring circuit can be shifted. By changing the duty cycle of the pulse waveform in incremental steps, certain problems can be avoided, such as erroneous QRS detect marks that are otherwise produced. The incremental steps in which the duty cycle of the pulse waveform is changed may be predetermined, or they may be adjusted according to feedback from the amplifier.

摘要翻译： 一种用于监测心电图波形并将心电图仪轨迹返回到诸如图表记录器条的显示器中间的方法和装置。 监视电路包括用于切换监视电路的频率响应曲线的放大器和开关。 在第一位置，开关使得监测电路具有缓慢的频率响应曲线，这允许精确地监测ECG波形。 在第二位置，开关使监视电路具有快速的频率响应曲线，这使得监视电路的放大器能够快速地脱离饱和。 当除颤或起搏脉冲被施加到被监视的患者时，监视电路的放大器变得饱和。 开关由微处理器提供的脉冲波形控制信号控制。 通过改变控制信号的占空比，可以改变监视电路的频率响应曲线。 通过以递增的步长改变脉冲波形的占空比，可以避免某些问题，例如否则产生的错误的QRS检测标记。 脉冲波形的占空比改变的增量步骤可以是预定的，或者可以根据来自放大器的反馈来调整。

公开(公告)号：US4993423A

公开(公告)日：1991-02-19

申请号：US464380

申请日：1990-01-12

申请人： John R. Stice

发明人： John R. Stice

IPC分类号： A61B5/0424 ,  G01R17/10

CPC分类号： A61B5/0424 ,  G01R17/105

摘要： A differential lead impedance comparison apparatus (10) senses lead impedance and compensates for patient-to-patient and electrode variability. A bridge circuit (12) is connected to one end of electrode conductors (22, 24 and 26) in an ECG Leads I configuration. The other end of the conductors (22, 24 and 26) are connected to a patient (18) via electrodes (RA, LA and LL). Leads formed in part by RA, LA and LL and the respective conductors (22, 24 and 26) have lead impedances (R.sub.b, R.sub.a, and R.sub.c). Constant current sources (11, 12 and 13) are connected to the conductors (22, 24 and 26) and supply constant AC currents (I.sub.1, I.sub.2 and I.sub.3). A first bridge output voltage (V.sub.M) is produced by I.sub.1 and a combination 32 of R.sub.a, R.sub.b, and R.sub.c. A second bridge output voltage (V.sub.P) is produced by I.sub.2 and a combination 34 of R.sub.a, R.sub.b, and R.sub.c. A differential amplifier circuit (14) differentially amplifies the V.sub.M and V.sub.P voltages to produce differential voltages (V.sub.OM and V.sub.OP). Demodulators (DM1 and DM2) demodulate V.sub.OM and V.sub.OP to produce differential impedance voltages (V.sub.1M and V.sub.1P). A first comparator (OA3) changes states and produces a high logic output when V.sub.1M equals or exceeds a first threshold level (V.sub.TH1). A second comparator (OA4) changes states and produces a high logic output when V.sub.1P equals or exceeds a second threshold level (V.sub.TH2). An exclusive OR gate (G1) produces a high logic output (V.sub.OUT) when one and only one of OA3 or OA4 produce a high logic output.

摘要翻译： 差分引线阻抗比较装置（10）感测引线阻抗并补偿患者与患者和电极的变异性。 桥接电路（12）以ECG引线I配置连接到电极导体（22,24和26）的一端。 导体（22,24和26）的另一端通过电极（RA，LA和LL）连接到患者（18）。 由RA，LA和LL部分形成的引线和相应的导体（22,24和26）具有引线阻抗（Rb，Ra和Rc）。 恒流源（11,12和13）连接到导体（22,24和26），并提供恒定的交流电流（I1，I2和I3）。 第一桥输出电压（VM）由I1和Ra，Rb和Rc的组合32产生。 第二桥输出电压（VP）由I2和Ra，Rb和Rc的组合34产生。 差分放大器电路（14）差分地放大VM和VP电压以产生差分电压（VOM和VOP）。 解调器（DM1和DM2）解调VOM和VOP以产生差分阻抗电压（V1M和V1P）。 当V1M等于或超过第一阈值电平（VTH1）时，第一比较器（OA3）改变状态并产生高逻辑输出。 当V1P等于或超过第二阈值电平（VTH2）时，第二比较器（OA4）改变状态并产生高逻辑输出。 当OA3或OA4中只有一个产生高逻辑输出时，异或门（G1）产生高逻辑输出（VOUT）。

公开(公告)号：US09162255B1

公开(公告)日：2015-10-20

申请号：US12686685

申请日：2010-01-13

申请人： John R. Stice ,  Yanwei Wang ,  Clinton T. Siedenburg ,  Andrew K. Lundberg ,  Justin Coughlin ,  Max E. Nielsen

发明人： John R. Stice ,  Yanwei Wang ,  Clinton T. Siedenburg ,  Andrew K. Lundberg ,  Justin Coughlin ,  Max E. Nielsen

IPC分类号： B06B1/02 ,  A61B8/00

CPC分类号： B06B1/0215 ,  A61B8/44 ,  A61B8/4444 ,  A61B8/4494 ,  A61B8/5207 ,  A61B8/5269 ,  A61B8/54 ,  B06B1/0207 ,  B06B1/0223 ,  B06B1/023 ,  G01S7/5202 ,  G01S7/52038 ,  G01S15/8963

摘要： The use of power-efficient transmitters to establish acoustic wave energy having low undesirable harmonics is achieved by adjusting the transmitter output waveform to minimize the undesirable harmonics. In one embodiment, both the timing and slope of the waveform edges are adjusted to produce the desired output waveform having little or no second harmonics. In the embodiment, output waveform timing adjustments on the order of fractions of the system clock interval are provided. This then allows for very fine control of a coarsely produced waveform. In one embodiment, the user can select the fine tuning to match the transmitter output signal to a particular load transducer.

摘要翻译： 通过调整发射机输出波形以最小化不期望的谐波来实现使用功率高效的发射机来建立具有低不期望的谐波的声波能量。 在一个实施例中，调整波形边缘的定时和斜率，以产生具有很少或不具有二次谐波的期望的输出波形。 在本实施例中，提供了系统时钟间隔分数的顺序的输出波形定时调整。 这样可以很好地控制粗略产生的波形。 在一个实施例中，用户可以选择微调以将发射机输出信号与特定负载传感器相匹配。

公开(公告)号：US06744390B1

公开(公告)日：2004-06-01

申请号：US09541460

申请日：2000-03-31

申请人： John R. Stice

发明人： John R. Stice

IPC分类号： H03M110

CPC分类号： H03M1/129

摘要： An analog to digital converter for input signals having a low frequency component (such as DC) upon which is superimposed an AC component, the magnitude of the AC component being less than or equal to one-half the span of the analog to digital converter.

摘要翻译： 一种用于具有低频分量（例如DC）的输入信号的模数转换器，其上叠加有AC分量，AC分量的幅度小于或等于模数转换器跨度的一半。

公开(公告)号：US4917099A

公开(公告)日：1990-04-17

申请号：US219349

申请日：1988-07-13

申请人： John R. Stice

发明人： John R. Stice

IPC分类号： A61B5/0424 ,  G01R17/10

CPC分类号： A61B5/0424 ,  G01R17/105

摘要： A differential lead impedance comparison apparatus (10) senses lead impedance and compensates for patient-to-patient and electrode variability. A bridge circuit (12) is connected to one end of electrode conductors (22, 24 and 26) in an ECG Leads I configuration. The other end of the conductors (22, 24 and 26) are connected to a patient (18) via electrodes (RA, LA and LL). Leads formed in part by RA, LA and LL and the respective conductors (22, 24 and 26) have lead impedances (R.sub.b, R.sub.a, and R.sub.c). Constant current sources (I1, I2 and I3) are connected to the conductors (22, 24, and 26) and supply constant AC currents (I.sub.1, I.sub.2 and I.sub.3). A first bridge output voltage (V.sub.M) is produced by I.sub.1 and a combination 32 of R.sub.a, R.sub.b, and R.sub.c. A second bridge output voltage (V.sub.P) is produced by I.sub.2 and a combination 34 of R.sub.a, R.sub.b, and R.sub.c. A differential amplifier circuit (14) differentially amplifies the V.sub.M and V.sub.P voltages to produce differential voltages (V.sub.OM and V.sub.OP). Demodulators (DM1 and DM2) demodulate V.sub.OM and V.sub.OP to produce differential impedance voltages (V.sub.1M and V.sub.1P). A first comparator (OA3) changes states and produces a high logic output when V.sub.1M equals or exceeds a first threshold level (V.sub.TH1). A second comparator (OA4) changes states and produces a high logic output when V.sub.1P equals or exceeds a second threshold level (V.sub.TH2). An exclusive OR gate (G1) produces a high logic output (V.sub.OUT) when one and only one of OA3 or OA4 produce a high logic output.

摘要翻译： 差分引线阻抗比较装置（10）感测引线阻抗并补偿患者与患者和电极的变异性。 桥接电路（12）以ECG引线I配置连接到电极导体（22,24和26）的一端。 导体（22,24和26）的另一端通过电极（RA，LA和LL）连接到患者（18）。 由RA，LA和LL部分形成的引线和相应的导体（22,24和26）具有引线阻抗（Rb，Ra和Rc）。 恒流源（I1，I2和I3）连接到导体（22,24和26），并提供恒定的交流电流（I1，I2和I3）。 第一桥输出电压（VM）由I1和Ra，Rb和Rc的组合32产生。 第二桥输出电压（VP）由I2和Ra，Rb和Rc的组合34产生。 差分放大器电路（14）差分地放大VM和VP电压以产生差分电压（VOM和VOP）。 解调器（DM1和DM2）解调VOM和VOP以产生差分阻抗电压（V1M和V1P）。 当V1M等于或超过第一阈值电平（VTH1）时，第一比较器（OA3）改变状态并产生高逻辑输出。 当V1P等于或超过第二阈值电平（VTH2）时，第二比较器（OA4）改变状态并产生高逻辑输出。 当OA3或OA4中只有一个产生高逻辑输出时，异或门（G1）产生高逻辑输出（VOUT）。