公开(公告)号：US20060133135A1

公开(公告)日：2006-06-22

申请号：US11017981

申请日：2004-12-20

申请人： Jonathan Lachman ,  Donald Weiss ,  John Wuu ,  Charles Morganti

发明人： Jonathan Lachman ,  Donald Weiss ,  John Wuu ,  Charles Morganti

IPC分类号： G11C11/00

CPC分类号： G11C11/417

摘要： An SRAM with reduced power consumption comprising N SRAM cells and peripheral circuitry that enables writing and reading any of the N SRAM cells. The number of cells, N, is a whole number. The voltage applied to the N SRAM cells is higher than the voltage applied to the peripheral circuitry.

摘要翻译： 具有降低功耗的SRAM，包括N个SRAM单元和能够写入和读取任何N个SRAM单元的外围电路。 单元格数N是整数。 施加到N个SRAM单元的电压高于施加到外围电路的电压。

公开(公告)号：US20050105323A1

公开(公告)日：2005-05-19

申请号：US10697679

申请日：2003-10-29

申请人： Todd Mellinger ,  J. Hill ,  Jonathan Lachman

发明人： Todd Mellinger ,  J. Hill ,  Jonathan Lachman

IPC分类号： G11C5/14 ,  G11C7/00 ,  G11C11/00

CPC分类号： G11C5/14

摘要： An embodiment of the invention provides a circuit for reducing power in memory cells. The input of the circuit is connected to the wordline of the memory cells. When the wordline is active, the output of the circuit applies a voltage near VDD to the positive voltage supply node of the memory cells. When the wordline is inactive, the output of the circuit applies a voltage that is reduced by at least one Vt from VDD to the positive voltage supply node of the memory cells.

公开(公告)号：US20070081409A1

公开(公告)日：2007-04-12

申请号：US11234480

申请日：2005-09-23

申请人： John Wuu ,  Jonathan Lachman ,  Donald Weiss

发明人： John Wuu ,  Jonathan Lachman ,  Donald Weiss

IPC分类号： G11C5/14

CPC分类号： G11C7/12 ,  G11C11/413 ,  G11C2207/2227

摘要： A method for reducing power in an SRAM is achieved by applying a first voltage to all bitlines of a section of the SRAM in standby operation and applying a second voltage to all the bitlines of a section of the SRAM in normal operation. The first voltage is not greater than the second voltage.

摘要翻译： 通过在待机操作中对SRAM的一部分的所有位线施加第一电压并且在正常操作中对SRAM的一部分的所有位线施加第二电压来实现用于降低SRAM中的功率的方法。 第一电压不大于第二电压。

公开(公告)号：US06775812B2

公开(公告)日：2004-08-10

申请号：US10197346

申请日：2002-07-17

申请人： John Andrew Francis Cloudman ,  Jonathan Lachman ,  Nicholas Michell

发明人： John Andrew Francis Cloudman ,  Jonathan Lachman ,  Nicholas Michell

IPC分类号： G06F1750

CPC分类号： H01L27/0203

摘要： An IC layout design process and system involves placing an adjustable capacitor cell having a plurality of sub-cells, each with a polysilicon shape disposed over a corresponding active area shape. The polysilicon shapes are electrically coupled to a first power rail and the active area shapes are electrically coupled to a second power rail. The sub-cells of the adjustable capacitor cell are operable to be modified to satisfy a density measurement associated with the IC's fabrication flow.

摘要翻译： IC布局设计过程和系统涉及放置具有多个子单元的可调节电容器单元，每个子单元具有设置在相应的有源区域形状上的多晶硅形状。 多晶硅形状电耦合到第一电力轨道，并且有源区域形状电耦合到第二电力轨道。 可调节电容器单元的子单元可操作以被修改以满足与IC制造流程相关联的密度测量。