公开(公告)号：US06452980B1

公开(公告)日：2002-09-17

申请号：US09480776

申请日：2000-01-10

申请人： Peter Zalud ,  Jonathan Schepps ,  Robert Evans ,  Min-Long Lin

发明人： Peter Zalud ,  Jonathan Schepps ,  Robert Evans ,  Min-Long Lin

IPC分类号： H04B1500

CPC分类号： G07C9/00111 ,  H03M5/12

摘要： An apparatus is described for reducing coherent signal interference between at least two bit streams framed with a common clock signal. The apparatus includes an internal clock signal generated from the common clock signal and a Manchester encoder for encoding the internal clock signal with a unique signature. Also included is a logic AND-gate for combining one bit stream of the two bit streams with the encoded clock signal to produce an encoded output signal. When the encoded output signal is combined with another of the two bit streams during transmission, individual bits of the combined bit streams are identifiable at a receiving end. The receiving end decodes the combined bit streams and properly discriminates between ONEs and ZEROs.

摘要翻译： 描述了一种用于减少用公共时钟信号构成的至少两个比特流之间的相干信号干扰的装置。 该装置包括从公共时钟信号产生的内部时钟信号和曼彻斯特编码器，用于对具有唯一签名的内部时钟信号进行编码。 还包括用于将两个比特流的一个比特流与编码的时钟信号组合以产生编码的输出信号的逻辑与门。 当编码的输出信号在传输期间与两个比特流中的另一个组合时，组合的比特流的各个比特在接收端是可识别的。 接收端解码组合的比特流，并正确区分ONE和ZERO。