公开(公告)号：US20090206386A1

公开(公告)日：2009-08-20

申请号：US12034316

申请日：2008-02-20

申请人： Nian Yang ,  Joon-Heong Ong ,  Jiani Zhang

发明人： Nian Yang ,  Joon-Heong Ong ,  Jiani Zhang

IPC分类号： H01L27/115 ,  H01L21/8247

CPC分类号： H01L27/11573 ,  H01L27/11565 ,  H01L2924/0002 ,  H01L2924/00

摘要： One embodiment of the present invention relates to a flash memory array. The flash memory array comprises at least two word lines of gate electrode material. At least one of the word lines is connected through a first metal level to a discharge circuit, while other word line(s) may connect to a discharge circuit through a first and second metal level. The memory array further comprises a shorting path between the word lines of the memory array. The shorting path is a high resistance layer of undoped gate electrode material. The resistance value of the gate electrode material is such that the word lines can be used to read, write, or erase without effecting each other, but that during the formation of a first metal level, as charges will build up on a first word line which requires a second metal level to connect to its discharge junction circuit, it will short the first word line to an adjacent second word line that has a connection to its junction circuit on the first metal level. Other methods and circuits are also disclosed.

摘要翻译： 本发明的一个实施例涉及闪存阵列。 闪存阵列包括栅电极材料的至少两个字线。 至少一个字线通过第一金属电平连接到放电电路，而其它字线可以通过第一和第二金属电平连接到放电电路。 存储器阵列还包括存储器阵列的字线之间的短路。 短路路径是未掺杂的栅电极材料的高电阻层。 栅极材料的电阻值使得字线可以用于读取，写入或擦除而不会彼此影响，但是在形成第一金属电平期间，由于电荷将在第一字线上积累 这要求第二金属电平连接到其放电结电路，它将使第一字线缩短到与第一金属电平上的结电路连接的相邻第二字线。 还公开了其它方法和电路。

公开(公告)号：US07948035B2

公开(公告)日：2011-05-24

申请号：US12034316

申请日：2008-02-20

申请人： Nian Yang ,  Joon-Heong Ong ,  Jiani Zhang

发明人： Nian Yang ,  Joon-Heong Ong ,  Jiani Zhang

IPC分类号： H01L23/62 ,  H01L29/792

CPC分类号： H01L27/11573 ,  H01L27/11565 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to a flash memory array. The flash memory array includes at least two word lines of gate electrode material. At least one of the word lines is connected through a first metal level to a discharge circuit, while other word line(s) may connect to a discharge circuit through a first and second metal level. The memory array further includes a shorting path between the word lines of the memory array. The shorting path is a high resistance layer of undoped gate electrode material. The resistance value of the gate electrode material is such that the word lines can be used to read, write, or erase without effecting each other, but that during the formation of a first metal level, as charges will build up on a first word line which requires a second metal level to connect to its discharge junction circuit, it will short the first word line to an adjacent second word line that has a connection to its junction circuit on the first metal level.

摘要翻译： 本发明涉及闪存阵列。 闪存阵列包括栅电极材料的至少两个字线。 至少一个字线通过第一金属电平连接到放电电路，而其它字线可以通过第一和第二金属电平连接到放电电路。 存储器阵列还包括存储器阵列的字线之间的短路路径。 短路路径是未掺杂的栅电极材料的高电阻层。 栅极材料的电阻值使得字线可以用于读取，写入或擦除而不会彼此影响，但是在形成第一金属电平期间，由于电荷将在第一字线上积累 这要求第二金属电平连接到其放电结电路，它将使第一字线缩短到与其第一金属电平上的结电路连接的相邻第二字线。