公开(公告)号：US5386526A

公开(公告)日：1995-01-31

申请号：US779388

申请日：1991-10-18

申请人： Samir Mitra ,  Renukanthan Raman ,  Joseph Petollno

发明人： Samir Mitra ,  Renukanthan Raman ,  Joseph Petollno

IPC分类号： G06F12/08 ,  G06F12/06 ,  G06F13/00

CPC分类号： G06F12/0859

摘要： A cache memory controller and an associated method for fetching data are utilized to reduce the idle time of a central processing unit (CPU) of a computer system. Control circuitry and a plurality of cache fill status registers are provided to a cache controller to enable a data word to be fetched and returned to the CPU while a cache memory fill initiated due to a prior cache miss is still in progress. The data word is returned if the data word is stored in a main memory location which corresponds to a memory block offset of a main memory block frame currently being mapped into the cache memory. The data word is retrieved and returned to the CPU simultaneous with its writing into the cache memory, if the data word has not been written into the cache memory; otherwise, the data word is retrieved and returned to the CPU at the next dead cycle. As a result, CPU idle time due to cache read misses is reduced.

摘要翻译： 利用高速缓冲存储器控制器和用于取出数据的关联方法来减少计算机系统的中央处理单元（CPU）的空闲时间。 控制电路和多个高速缓存填充状态寄存器被提供给高速缓存控制器，以使数据字被取出并返回到CPU，同时由于先前的高速缓存未命中而启动的高速缓存存储器填充仍在进行中。 如果数据字被存储在与当前被映射到高速缓冲存储器中的主存储器块帧的存储器块偏移相对应的主存储器位置中，则返回数据字。 如果数据字未写入高速缓冲存储器，数据字被读取并返回到CPU同时写入高速缓冲存储器; 否则，数据字被检索并在下一个死循环返回给CPU。 结果，由于缓存读取未命中而导致的CPU空闲时间减少。