公开(公告)号：US20080282304A1

公开(公告)日：2008-11-13

申请号：US11976556

申请日：2007-10-25

申请人： Ju Lung Fann ,  Chun Fu Shen ,  Shih Yu Hsu

发明人： Ju Lung Fann ,  Chun Fu Shen ,  Shih Yu Hsu

IPC分类号： H04N7/173

CPC分类号： H04N19/59 ,  H04N19/423 ,  H04N19/436 ,  H04N19/61

摘要： A module for generating real-time, multiple-resolution video streams and the architecture thereof are disclosed. A module for generating multiple-resolution video streams as well as the architecture thereof for use with a video encoder includes a system bus, an external memory and a main processor. The main processor and the external memory are coupled to the system bus. The main processor includes a microprocessor, a main arithmetic unit and a secondary arithmetic unit. By applying the present invention, a less time-consuming arithmetic module can synchronously perform together with a more time-consuming arithmetic module, thereby reducing idle time and increasing hardware efficiency and parallelism.

摘要翻译： 公开了一种用于生成实时多分辨率视频流的模块及其结构。 用于产生多分辨率视频流的模块及其与视频编码器一起使用的架构包括系统总线，外部存储器和主处理器。 主处理器和外部存储器耦合到系统总线。 主处理器包括微处理器，主运算单元和辅助运算单元。 通过应用本发明，更耗时的算术模块可以与更耗时的算术模块同时执行，从而减少空闲时间并提高硬件效率和并行性。

公开(公告)号：US08045613B2

公开(公告)日：2011-10-25

申请号：US11976556

申请日：2007-10-25

申请人： Ju Lung Fann ,  Chun Fu Shen ,  Shih Yu Hsu

发明人： Ju Lung Fann ,  Chun Fu Shen ,  Shih Yu Hsu

IPC分类号： H04N7/12

CPC分类号： H04N19/59 ,  H04N19/423 ,  H04N19/436 ,  H04N19/61

摘要： A module for generating real-time, multiple-resolution video streams and the architecture thereof are disclosed. A module for generating multiple-resolution video streams as well as the architecture thereof for use with a video encoder includes a system bus, an external memory and a main processor. The main processor and the external memory are coupled to the system bus. The main processor includes a microprocessor, a main arithmetic unit and a secondary arithmetic unit. By applying the present invention, a less time-consuming arithmetic module can synchronously perform together with a more time-consuming arithmetic module, thereby reducing idle time and increasing hardware efficiency and parallelism.

摘要翻译： 公开了一种用于生成实时多分辨率视频流的模块及其结构。 用于产生多分辨率视频流的模块及其与视频编码器一起使用的架构包括系统总线，外部存储器和主处理器。 主处理器和外部存储器耦合到系统总线。 主处理器包括微处理器，主运算单元和辅助运算单元。 通过应用本发明，更耗时的算术模块可以与更耗时的算术模块同时执行，从而减少空闲时间并提高硬件效率和并行性。

公开(公告)号：US20060161698A1

公开(公告)日：2006-07-20

申请号：US11126357

申请日：2005-05-11

申请人： Chun-Fu Shen ,  Ju-Lung Fann

发明人： Chun-Fu Shen ,  Ju-Lung Fann

IPC分类号： G06F5/00 ,  G06F13/40

CPC分类号： G06F13/1678 ,  G06F13/4018

摘要： Provided is an external memory accessing architecture for use with IC comprising a first bus connected to an external memory and having n-bit data width; a first buffer unit of k serially connected first buffers each having n-bit data width, a first one of the first buffers connected to the external memory via the first bus; a second buffer unit comprising a second buffer having k*n-bit data width, the second buffer connected to the first buffers; a second bus connected to the second buffer for transferring k*n-bit data; an output unit connected to the second buffer unit and comprising a multiplexer; and a controller connected to the output unit, the second bus, and the external memory respectively such that the controller is able to read data from the external memory or transfer data thereto via the second bus and at least one control signal in higher transfer rate.

摘要翻译： 提供了一种用于IC的外部存储器访问架构，其包括连接到外部存储器并具有n位数据宽度的第一总线; k个串行连接的第一缓冲器的第一缓冲单元，每个具有n位数据宽度，第一缓冲器中的第一缓冲器经由第一总线连接到外部存储器; 第二缓冲单元，包括具有k * n位数据宽度的第二缓冲器，所述第二缓冲器连接到所述第一缓冲器; 连接到第二缓冲器的用于传送k * n位数据的第二总线; 连接到第二缓冲单元并包括多路复用器的输出单元; 以及分别连接到输出单元，第二总线和外部存储器的控制器，使得控制器能够从外部存储器读取数据或经由第二总线传送数据，并且以更高的传输速率传送至少一个控制信号。