公开(公告)号：US20050122765A1

公开(公告)日：2005-06-09

申请号：US10993202

申请日：2004-11-18

申请人： Judith Allen ,  Dennis Wilson ,  William Kraus ,  Lark Lehman

发明人： Judith Allen ,  Dennis Wilson ,  William Kraus ,  Lark Lehman

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： A reference cell layout for use in a 1T/1C ferroelectric memory array includes a transistor of a first polarity type having a gate coupled to a reference word line and a current path coupled between a bit line and an internal cell node, a transistor of a second polarity type having a gate coupled to a pre-charge line and a current path coupled between a source of power supply voltage and the internal cell node, a shunt reference word line extending across the reference cell that is electrically isolated from the reference word line, the pre-charge line and the transistors within the physical boundary of the memory cell, and a ferroelectric capacitor coupled between the internal cell node and a reference plate line.

摘要翻译： 用于1T / 1C铁电存储器阵列的参考单元布局包括具有耦合到参考字线的栅极和耦合在位线和内部单元节点之间的电流通路的第一极性类型的晶体管， 具有耦合到预充电线的栅极和耦合在电源电压源和内部单元节点之间的电流路径的第二极性类型，跨越参考电池延伸的分流参考字线，其与参考字线电隔离 ，预充电线和存储单元的物理边界内的晶体管，以及耦合在内部单元节点和参考板线之间的铁电电容器。