公开(公告)号：US5530616A

公开(公告)日：1996-06-25

申请号：US341001

申请日：1994-11-17

申请人： Tetsuo Kitabayashi ,  Atsushi Obara ,  Jun Miyagi ,  Yasumi Sago ,  Masami Sasaki

发明人： Tetsuo Kitabayashi ,  Atsushi Obara ,  Jun Miyagi ,  Yasumi Sago ,  Masami Sasaki

IPC分类号： B23Q3/15 ,  H01L21/683 ,  H02N13/00

CPC分类号： H02N13/00 ,  H01L21/6831 ,  H01L21/6833

摘要： An electrostatic chuck for electrostatically clamping a semiconductor wafer while minimizing any plane temperature difference thereof has a dielectric layer joined to a metal plate and an inner electrode disposed in the di-electric layer. The dielectric layer has a raised outer rim disposed on an upper surface thereof along an outer peripheral edge thereof, and a plurality of protrusions disposed on the upper surface radially inwardly of the outer rim, the protrusions having upper surfaces for clamping the semiconductor wafer in direct contact therewith. The volume resistivity of the dielectric layer is 10.sup.9 .OMEGA.m or less, and Rmax (maximum height) of the clamping surfaces of the protrusions 5 is 2.0 .mu.m or less and or Ra (center-line average roughness) thereof is 0.25 .mu.m or less. The ratio of the total area of the clamping surfaces of the protrusions to the entire area of the upper surface of the dielectric layer is equal to or greater than 1% and less than 10%.

摘要翻译： 用于静电夹持半导体晶片同时最小化其平面温度差的静电卡盘具有连接到设置在二电层中的金属板和内部电极的电介质层。 电介质层具有沿着其外周边缘设置在其上表面上的凸起的外边缘，以及设置在外边缘的径向内侧的上表面上的多个突起，所述突起具有用于将半导体晶片直接夹持的上表面 与其接触。 电介质层的体积电阻率为10 10Ω·m以下，突起5的夹持面的Rmax（最大高度）为2.0μm以下，Ra（中心线平均粗糙度）为0.25μm， 减。 突起的夹持表面的总面积与介电层的上表面的整个面积的比率等于或大于1％且小于10％。