公开(公告)号：US20240137431A1

公开(公告)日：2024-04-25

申请号：US18155048

申请日：2023-01-16

申请人： Chung Yuan Christian University ,  KGI Securities Co. Ltd.

发明人： Yu-Kuen Lai ,  Chao-Lin Wang ,  He-Ping Li ,  Cheng-Han Chuang ,  Kai-Po Chang

IPC分类号： H04L69/163 ,  H04L69/22

CPC分类号： H04L69/163 ,  H04L69/22

摘要： A packet sorting and reassembly circuit module, including a header parser, an information processing circuit, at least one state tracking and reassembly circuit, and an output arbiter, is provided. The header parser is configured to analyze multiple first packet segments to obtain header information corresponding to a first network packet, wherein the first network packet is transmitted based on a transmission control protocol (TCP) communication protocol. The information processing circuit is configured to transmit the first packet segments and sideband information corresponding to the first packet segments to a first state tracking and reassembly circuit among the at least one state tracking and reassembly circuit according to the header information. The first state tracking and reassembly circuit is configured to reassemble and sort the first packet segments according to the sideband information. The output arbiter is configured to output the first packet segments according to a sorting result.

公开(公告)号：US20240236212A9

公开(公告)日：2024-07-11

申请号：US18155048

申请日：2023-01-16

申请人： Chung Yuan Christian University ,  KGI Securities Co. Ltd.

发明人： Yu-Kuen Lai ,  Chao-Lin Wang ,  He-Ping Li ,  Cheng-Han Chuang ,  Kai-Po Chang

IPC分类号： H04L69/163 ,  H04L69/22

CPC分类号： H04L69/163 ,  H04L69/22

摘要： A packet sorting and reassembly circuit module, including a header parser, an information processing circuit, at least one state tracking and reassembly circuit, and an output arbiter, is provided. The header parser is configured to analyze multiple first packet segments to obtain header information corresponding to a first network packet, wherein the first network packet is transmitted based on a transmission control protocol (TCP) communication protocol. The information processing circuit is configured to transmit the first packet segments and sideband information corresponding to the first packet segments to a first state tracking and reassembly circuit among the at least one state tracking and reassembly circuit according to the header information. The first state tracking and reassembly circuit is configured to reassemble and sort the first packet segments according to the sideband information. The output arbiter is configured to output the first packet segments according to a sorting result.

公开(公告)号：US11979479B1

公开(公告)日：2024-05-07

申请号：US18155048

申请日：2023-01-16

申请人： Chung Yuan Christian University ,  KGI Securities Co. Ltd.

发明人： Yu-Kuen Lai ,  Chao-Lin Wang ,  He-Ping Li ,  Cheng-Han Chuang ,  Kai-Po Chang

IPC分类号： H04L69/163 ,  H04L69/22

CPC分类号： H04L69/163 ,  H04L69/22

摘要： A packet sorting and reassembly circuit module, including a header parser, an information processing circuit, at least one state tracking and reassembly circuit, and an output arbiter, is provided. The header parser is configured to analyze multiple first packet segments to obtain header information corresponding to a first network packet, wherein the first network packet is transmitted based on a transmission control protocol (TCP) communication protocol. The information processing circuit is configured to transmit the first packet segments and sideband information corresponding to the first packet segments to a first state tracking and reassembly circuit among the at least one state tracking and reassembly circuit according to the header information. The first state tracking and reassembly circuit is configured to reassemble and sort the first packet segments according to the sideband information. The output arbiter is configured to output the first packet segments according to a sorting result.