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公开(公告)号:US12125426B2
公开(公告)日:2024-10-22
申请号:US18210960
申请日:2023-06-16
Inventor: Hyung Gun Ma , Gyu Wan Lim , Gyeong Gu Kang , Hyun Sik Kim , Keum Dong Jung , Moon Jae Jeong
IPC: G09G3/20 , G06F3/044 , G09G3/3208 , H10K59/40
CPC classification number: G09G3/20 , G06F3/044 , G09G3/3208 , G09G2300/0828 , G09G2300/0852 , G09G2300/0871 , G09G2310/027 , G09G2310/0291 , G09G2330/028 , H10K59/40
Abstract: A data driving circuit includes: a resistor string in which a plurality of resistors are connected in series; and a plurality of data channels connected to a high voltage node, intermediate voltage nodes, and a low voltage node of the resistor string and configured to convert a digital data signal into an analog data voltage. Each of the plurality of data channels includes: a main digital-to-analog converter connected to the high voltage node, the intermediate voltage nodes, and the low voltage node, a multiplier connected to an output terminal of the main digital-to-analog converter, a sub digital-to-analog converter connected to some of the high voltage node, the intermediate voltage nodes, and the low voltage node, and a voltage synthesizer connected to an output terminal of the multiplier and an output terminal of the sub digital-to-analog converter.
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公开(公告)号:US11721265B1
公开(公告)日:2023-08-08
申请号:US17985554
申请日:2022-11-11
Inventor: Hyung Gun Ma , Gyu Wan Lim , Gyeong Gu Kang , Hyun Sik Kim , Keum Dong Jung , Moon Jae Jeong
IPC: G09G3/20 , G06F3/044 , G09G3/3208 , H10K59/40
CPC classification number: G09G3/20 , G06F3/044 , G09G3/3208 , G09G2300/0828 , G09G2300/0852 , G09G2300/0871 , G09G2310/027 , G09G2310/0291 , G09G2330/028 , H10K59/40
Abstract: A data driving circuit includes: a resistor string in which a plurality of resistors are connected in series; and a plurality of data channels connected to a high voltage node, intermediate voltage nodes, and a low voltage node of the resistor string and configured to convert a digital data signal into an analog data voltage. Each of the plurality of data channels includes: a main digital-to-analog converter connected to the high voltage node, the intermediate voltage nodes, and the low voltage node, a multiplier connected to an output terminal of the main digital-to-analog converter, a sub digital-to-analog converter connected to some of the high voltage node, the intermediate voltage nodes, and the low voltage node, and a voltage synthesizer connected to an output terminal of the multiplier and an output terminal of the sub digital-to-analog converter.
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公开(公告)号:US20230326384A1
公开(公告)日:2023-10-12
申请号:US18210960
申请日:2023-06-16
Inventor: Hyung Gun MA , Gyu Wan LIM , Gyeong Gu KANG , Hyun Sik KIM , Keum Dong JUNG , Moon Jae JEONG
IPC: G09G3/20
CPC classification number: G09G3/20 , G09G3/3208 , G09G2310/027 , G09G2300/0871
Abstract: A data driving circuit includes: a resistor string in which a plurality of resistors are connected in series; and a plurality of data channels connected to a high voltage node, intermediate voltage nodes, and a low voltage node of the resistor string and configured to convert a digital data signal into an analog data voltage. Each of the plurality of data channels includes: a main digital-to-analog converter connected to the high voltage node, the intermediate voltage nodes, and the low voltage node, a multiplier connected to an output terminal of the main digital-to-analog converter, a sub digital-to-analog converter connected to some of the high voltage node, the intermediate voltage nodes, and the low voltage node, and a voltage synthesizer connected to an output terminal of the multiplier and an output terminal of the sub digital-to-analog converter.
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公开(公告)号:US20230260441A1
公开(公告)日:2023-08-17
申请号:US17985554
申请日:2022-11-11
Inventor: Hyung Gun Ma , Gyu Wan Lim , Gyeong Gu Kang , Hyun Sik Kim , Keum Dong Jung , Moon Jae Jeong
IPC: G09G3/20
CPC classification number: G09G3/20 , H01L27/323
Abstract: A data driving circuit includes: a resistor string in which a plurality of resistors are connected in series; and a plurality of data channels connected to a high voltage node, intermediate voltage nodes, and a low voltage node of the resistor string and configured to convert a digital data signal into an analog data voltage. Each of the plurality of data channels includes: a main digital-to-analog converter connected to the high voltage node, the intermediate voltage nodes, and the low voltage node, a multiplier connected to an output terminal of the main digital-to-analog converter, a sub digital-to-analog converter connected to some of the high voltage node, the intermediate voltage nodes, and the low voltage node, and a voltage synthesizer connected to an output terminal of the multiplier and an output terminal of the sub digital-to-analog converter.
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