公开(公告)号：US5391509A

公开(公告)日：1995-02-21

申请号：US164954

申请日：1993-12-10

申请人： Naoki Matsukawa ,  Makoto Mizuno ,  Katsuhiro Shimazu

发明人： Naoki Matsukawa ,  Makoto Mizuno ,  Katsuhiro Shimazu

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L21/2652

摘要： Impurities are introduced into a semiconductor substrate by using a gate electrode formed on the semiconductor substrate through an oxide film as a mask, and low concentration impurity regions are formed. Then, side walls are formed on the gate electrode. Next, after an insulating film is formed on the whole surface of the substrate by a CVD method, impurities are introduced by using the gate electrode and the side walls as a mask, and high concentration impurity regions are formed. Then, a thermal treatment of the substrate is performed, and after the low concentration impurity regions and the high concentration impurity regions are crystallized, an interlayer insulating film is formed.

摘要翻译： 通过使用通过氧化膜形成在半导体衬底上的栅电极作为掩模，将杂质引入到半导体衬底中，形成低浓度杂质区。 然后，在栅电极上形成侧壁。 接下来，在通过CVD法在基板的整个表面上形成绝缘膜之后，通过使用栅电极和侧壁作为掩模来引入杂质，形成高浓度杂质区。 然后，进行基板的热处理，在低浓度杂质区域和高浓度杂质区域结晶后，形成层间绝缘膜。

公开(公告)号：US20210056444A1

公开(公告)日：2021-02-25

申请号：US16545708

申请日：2019-08-20

申请人： Katsuhiro SHIMAZU

发明人： Katsuhiro SHIMAZU

IPC分类号： G06N5/04 ,  G06N5/00 ,  G06N20/00

摘要： A method comprising, by a processing unit and a memory: obtaining a training set of data; dividing sets of data into a plurality of groups, wherein all sets of data for which feature values meet at least one similarity criterion, are in the same group, storing in a reduced training set of data, for each group, at least one aggregated set of data, wherein, for a plurality of the groups, a number of aggregated sets of data is less than a number of the sets of data of the group, wherein the reduced training set of data is suitable to be used in a classification algorithm for determining a relationship between the at least one label and the features of the electronic items, thereby reducing computation complexity when processing the reduced training set of data, compared to processing the training set of data.

公开(公告)号：US5290717A

公开(公告)日：1994-03-01

申请号：US896571

申请日：1992-06-10

申请人： Katsuhiro Shimazu

发明人： Katsuhiro Shimazu

IPC分类号： H01L21/265 ,  H01L21/266 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L29/66575 ,  H01L21/265 ,  H01L21/266

摘要： A method of manufacturing a semiconductor device including a MOS transistor, wherein a second resist pattern having openings respectively defining gate, source, and drain regions is formed while leaving a first resist pattern on a gate material film, i.e., a polycrystalline silicon film, which is used to form a gate electrode. Impurities are implanted into the source and drain regions by using the first and second resist patterns as a mask. The impurities are stopped in the inside of the first resist pattern on the gate and are not implanted into the gate.

摘要翻译： 一种制造包括MOS晶体管的半导体器件的方法，其中形成具有分别限定栅极，源极和漏极区域的开口的第二抗蚀剂图案，同时在栅极材料膜（即，多晶硅膜）上留下第一抗蚀剂图案，其中多晶硅膜 用于形成栅电极。 通过使用第一和第二抗蚀剂图案作为掩模将杂质注入源区和漏区。 杂质停留在栅极上的第一抗蚀剂图案的内部，并且不被注入到栅极中。