公开(公告)号：US20140068125A1

公开(公告)日：2014-03-06

申请号：US13599249

申请日：2012-08-30

申请人： Sakthivel K. Pullagoundapatti ,  Krishna V. Bhandi ,  Claus Pribbernow

发明人： Sakthivel K. Pullagoundapatti ,  Krishna V. Bhandi ,  Claus Pribbernow

IPC分类号： G06F13/00

CPC分类号： G06F13/404 ,  G06F13/1663

摘要： Aspects of the disclosure pertain to a system and method for promoting memory throughput improvement in a multi-processor system. The system and method implement address interleaving for promoting memory throughput improvement. The system and method cause memory access requests to be selectively routed from master devices to slave devices based upon a determined value of a selected bit of an address specified in the memory access request.

摘要翻译： 本公开的方面涉及用于在多处理器系统中促进存储器吞吐量改进的系统和方法。 该系统和方法实现地址交织，以促进内存吞吐量的提高。 基于在存储器访问请求中指定的地址的选定位的确定值，系统和方法使得存储器访问请求被选择性地从主设备路由到从设备。