Input jitter attenuation in a phase-locked loop
    1.
    发明授权
    Input jitter attenuation in a phase-locked loop 有权
    在锁相环中输入抖动衰减

    公开(公告)号:US06703878B2

    公开(公告)日:2004-03-09

    申请号:US10206778

    申请日:2002-07-25

    IPC分类号: H03L700

    CPC分类号: H03L7/18 H03L7/093 H03L7/1978

    摘要: To attenuate the effects of phase noise and input jitter introduced in the reference frequency of the PLL, the zeros of the forward path transfer function are removed. As a result, the forward path does not amplify any phase noise or input jitter appearing in the reference frequency. However, overall loop stability is maintained by placing the zeros in the feedback path of the PLL. A discriminator may be placed in the feedback path to introduce the zero in the loop gain transfer function and provide stability.

    摘要翻译: 为了衰减在PLL的参考频率中引入的相位噪声和输入抖动的影响,前向路径传递函数的零被去除。 因此,正向通路不会放大出现在参考频率中的任何相位噪声或输入抖动。 然而,通过将零置于PLL的反馈路径中来保持总体环路稳定性。 可以在反馈路径中放置鉴别器以将零引入环路增益传递函数并提供稳定性。