公开(公告)号：US07961263B2

公开(公告)日：2011-06-14

申请号：US10891117

申请日：2004-07-15

申请人： Jun-Ho Song ,  Kyeong-Nam Lee

发明人： Jun-Ho Song ,  Kyeong-Nam Lee

IPC分类号： G02F1/136 ,  G02F1/1333 ,  G02F1/1343

CPC分类号： G02F1/136204

摘要： A liquid crystal display can include a gate wire including a gate line, a gate pad and a gate line connector and a common signal wire formed on a substrate. A gate insulating layer may be formed over the gate wire and the common signal wire. A semiconductor layer and an ohmic contact layer may be sequentially formed on the gate insulating layer, a data wire including a source and a drain electrode, a data line, a data pad, a data line connector and a pixel electrode may be formed thereon. The thickness of the data wire and the pixel electrode may be equal to or less than 500 Å.

摘要翻译： 液晶显示器可以包括栅极线，其包括栅极线，栅极焊盘和栅极线连接器以及形成在基板上的公共信号线。 栅极绝缘层可以形成在栅极线和公共信号线上。 可以在栅极绝缘层上顺序地形成半导体层和欧姆接触层，可以在其上形成包括源极和漏极的数据线，数据线，数据焊盘，数据线连接器和像素电极。 数据线和像素电极的厚度可以等于或小于500。

公开(公告)号：US06856372B2

公开(公告)日：2005-02-15

申请号：US10140139

申请日：2002-05-07

申请人： Jun-Ho Song ,  Kyeong-Nam Lee

发明人： Jun-Ho Song ,  Kyeong-Nam Lee

IPC分类号： G02F1/1362 ,  G02F1/1343 ,  G02F1/136

CPC分类号： G02F1/136204

摘要： A gate wire including a gate line, a gate electrode, a gate pad and a gate line connector and a common signal wire are formed on a substrate, and a gate insulating layer is formed over the gate wire and the common signal wire. A semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating layer, a data wire including a source and a drain electrode, a data line, a data pad and a data line connector and a pixel electrode are formed thereon. The thickness of the data wire and the pixel electrode is equal to or less than 500 Å. A passivation layer is formed on the data wire and the pixel electrode, a redundant data wire is formed thereon, and a redundant gate pad and a redundant gate line connector are formed. The redundant data wire is electrically connected to the data wire through the contact holes in the passivation layer, and the redundant gate pad and the redundant gate line connector are electrically connected to the gate pad and the gate line connector respectively through the contact holes in the passivation layer and the gate insulating layer. The redundant gate line connector and the redundant data line connector are connected to each other to short the gate and the data wires. After an alignment layer is formed and rubbed, the edge of the panel is cut away to remove the gate line connector and the data line connector.

摘要翻译： 在基板上形成包括栅极线，栅电极，栅极焊盘和栅极线连接器以及公共信号线的栅极线，并且在栅极线和公共信号线上形成栅极绝缘层。 在栅极绝缘层上依次形成半导体层和欧姆接触层，在其上形成包括源极和漏极的数据线，数据线，数据焊盘和数据线连接器以及像素电极。 数据线和像素电极的厚度等于或小于500。 在数据线和像素电极上形成钝化层，在其上形成冗余数据线，形成冗余栅极焊盘和冗余栅极线连接器。 冗余数据线通过钝化层中的接触孔与数据线电连接，并且冗余栅极焊盘和冗余栅线连接器分别通过栅极接线孔和栅极线连接器中的接触孔电连接 钝化层和栅极绝缘层。 冗余栅极线连接器和冗余数据线连接器彼此连接以缩短栅极和数据线。 在形成并摩擦对准层之后，切割面板的边缘以移除栅极线连接器和数据线连接器。

公开(公告)号：US6133977A

公开(公告)日：2000-10-17

申请号：US212161

申请日：1998-12-15

申请人： Kyeong-Nam Lee ,  Woon-Yong Park

发明人： Kyeong-Nam Lee ,  Woon-Yong Park

IPC分类号： G02F1/1343 ,  G02F1/1362

CPC分类号： G02F1/13458 ,  G02F1/134363

摘要： A gate wire including a gate line, a gate electrode and a gate pad, and a common signal wire including a plurality of common electrodes and a common signal line connecting the common electrodes are formed on a substrate. A first data pattern including a first data line defining a pixel region along with the gate line, a source and drain electrode, a first data pad and a pixel wire parallel to the common electrodes is formed on a gate insulating layer covering the gate wire and the common signal wire. A second data pattern including a second data line, a second data pad and a supplementary gate pad, which are connected to the first data line, the first data pad and the gate pad respectively through contact holes formed in a passivation layer, is on the passivation layer. Here, the first or the second data line and the common electrodes adjacent thereto overlap each other to prevent the light leakage near the edges of the pixel region and to increase the aperture ratio of the LCD. The data pattern may have a double-layered structure in order to prevent its disconnections, and the short between the data pattern and the common electrodes adjacent to the second data line is reduced by disposing the gate insulating layer and the passivation layer therebetween. The upper layer of the first or the second data pad and the supplementary gate pad are made of either chromium, molybdenum, molybdenum alloy or ITO to improve the high reliability of the contact property.

公开(公告)号：US06466289B1

公开(公告)日：2002-10-15

申请号：US09643497

申请日：2000-08-22

申请人： Kyeong-Nam Lee ,  Woon-Yong Park

发明人： Kyeong-Nam Lee ,  Woon-Yong Park

IPC分类号： G02F11343

CPC分类号： G02F1/13458 ,  G02F1/134363

摘要： A gate wire including a gate line, a gate electrode and a gate pad, and a common signal wire including a plurality of common electrodes and a common signal line connecting the common electrodes are formed on a substrate. A first data pattern including a first data line defining a pixel region along with the gate line, a source and drain electrode, a first data pad and a pixel wire parallel to the common electrodes is formed on a gate insulating layer covering the gate wire and the common signal wire. A second data pattern including a second data line, a second data pad and a supplementary gate pad, which are connected to the first data line, the first data pad and the gate pad respectively through contact holes formed in a passivation layer, is on the passivation layer. Here, the first or the second data line and the common electrodes adjacent thereto overlap each other to prevent the light leakage near the edges of the pixel region and to increase the aperture ratio of the LCD. The data pattern may have a double-layered structure in order to prevent its disconnections, and the short between the data pattern and the common electrodes adjacent to the second data line is reduced by disposing the gate insulating layer and the passivation layer therebetween. The upper layer of the first or the second data pad and the supplementary gate pad are made of either chromium, molybdenum, molybdenum alloy or ITO to improve the high reliability of the contact property.

摘要翻译： 在基板上形成包括栅极线，栅极电极和栅极焊盘的栅极线，以及包括多个公共电极和公共信号线的公共信号线。 在覆盖栅极线的栅绝缘层上形成第一数据图案，该第一数据图形包括与栅极线一起形成像素区域的第一数据线，平行于公共电极的源极和漏极，第一数据焊盘和像素引线， 公共信号线。 在第一数据线上，分别通过形成在钝化层中的接触孔连接到第一数据线，第一数据焊盘和栅极焊盘的第二数据线，第二数据焊盘和辅助栅极焊盘的第二数据模式在 钝化层。 这里，与其相邻的第一或第二数据线和公共电极彼此重叠以防止在像素区域的边缘附近的光泄漏并且增加LCD的开口率。 数据图案可以具有双层结构以防止其断开，并且通过在其间设置栅极绝缘层和钝化层来减小数据图案和与第二数据线相邻的公共电极之间的短路。 第一或第二数据焊盘的上层和辅助栅极焊盘由铬，钼，钼合金或ITO制成，以提高接触性能的高可靠性。

公开(公告)号：US06411358B1

公开(公告)日：2002-06-25

申请号：US09804350

申请日：2001-03-12

申请人： Jun-Ho Song ,  Kyeong-Nam Lee

发明人： Jun-Ho Song ,  Kyeong-Nam Lee

IPC分类号： G02F11343

摘要： A gate wire including a gate line, a gate electrode, a gate pad and a gate line connector and a common signal wire are formed on a substrate, and a gate insulating layer is formed over the gate wire and the common signal wire. A semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating layer, a data wire including a source and a drain electrode, a data line, a data pad and a data line connector and a pixel electrode are formed thereon. The thickness of the data wire and the pixel electrode is equal to or less than 500 Å. A passivation layer is formed on the data wire and the pixel electrode, a redundant data wire is formed thereon, and a redundant gate pad and a redundant gate line connector are formed. The redundant data wire is electrically connected to the data wire through the contact holes in the passivation layer, and the redundant gate pad and the redundant gate line connector are electrically connected to the gate pad and the gate line connector respectively through the contact holes in the passivation layer and the gate insulating layer. The redundant gate line connector and the redundant data line connector are connected to each other to short the gate and the data wires. After an alignment layer is formed and rubbed, the edge of the panel is cut away to remove the gate line connector and the data line connector.

公开(公告)号：US06215541B1

公开(公告)日：2001-04-10

申请号：US09106226

申请日：1998-06-29

申请人： Jun-Ho Song ,  Kyeong-Nam Lee

发明人： Jun-Ho Song ,  Kyeong-Nam Lee

IPC分类号： G02F11343

CPC分类号： G02F1/136204

摘要： A gate wire including a gate line, a gate electrode, a gate pad and a gate line connector and a common signal wire are formed on a substrate, and a gate insulating layer is formed over the gate wire and the common signal wire. A semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating layer, a data wire including a source and a drain electrode, a data line, a data pad and a data line connector and a pixel electrode are formed thereon. The thickness of the data wire and the pixel electrode is equal to or less than 500 Å. A passivation layer is formed on the data wire and the pixel electrode, a redundant data wire is formed thereon, and a redundant gate pad and a redundant gate line connector are formed. The redundant data wire is electrically connected to the data wire through the contact holes in the passivation layer, and the redundant gate pad and the redundant gate line connector are electrically connected to the gate pad and the gate line connector respectively through the contact holes in the passivation layer and the gate insulating layer. The redundant gate line connector and the redundant data line connector are connected to each other to short the gate and the data wires. After an alignment layer is formed and rubbed, the edge of the panel is cut away to remove the gate line connector and the data line connector.

摘要翻译： 在基板上形成包括栅极线，栅电极，栅极焊盘和栅极线连接器以及公共信号线的栅极线，并且在栅极线和公共信号线上形成栅极绝缘层。 在栅极绝缘层上依次形成半导体层和欧姆接触层，在其上形成包括源极和漏极的数据线，数据线，数据焊盘和数据线连接器以及像素电极。 数据线和像素电极的厚度等于或小于500。 在数据线和像素电极上形成钝化层，在其上形成冗余数据线，形成冗余栅极焊盘和冗余栅极线连接器。 冗余数据线通过钝化层中的接触孔与数据线电连接，并且冗余栅极焊盘和冗余栅线连接器分别通过栅极接线孔和栅极线连接器中的接触孔电连接 钝化层和栅极绝缘层。 冗余栅极线连接器和冗余数据线连接器彼此连接以缩短栅极和数据线。 在形成并摩擦对准层之后，切割面板的边缘以移除栅极线连接器和数据线连接器。