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1.发明申请Methods and systems for providing variable clock rates and data rates for a serdes 有权为serdes提供可变时钟速率和数据速率的方法和系统公开(公告)号：US20090086847A1
公开(公告)日：2009-04-02
申请号：US11904875
申请日：2007-09-28
IPC分类号： H04L27/00
摘要： A method and apparatus for varying an output clock signal frequency to match the frequency of an output data signal frequency for a SERDES circuit while maintaining a constant input clock frequency is shown. According to this method and apparatus, a PMA rate signal may control the frequency of the output clock while a datastrobe signal may be used to control the frequency of the data signal. Accordingly, the apparatus and methods may be used to produce an output data signal and a clock signal having frequencies that may be lower than the frequency of the input clock signal.
摘要翻译： 示出了用于改变输出时钟信号频率以匹配SERDES电路的输出数据信号频率的频率同时保持恒定的输入时钟频率的方法和装置。 根据该方法和装置，PMA速率信号可以控制输出时钟的频率，同时可以使用数据探测器信号来控制数据信号的频率。 因此，该装置和方法可用于产生具有可能低于输入时钟信号的频率的频率的输出数据信号和时钟信号。
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2.发明授权Methods and systems for providing variable clock rates and data rates for a SERDES 有权为SERDES提供可变时钟速率和数据速率的方法和系统公开(公告)号：US07983374B2
公开(公告)日：2011-07-19
申请号：US11904875
申请日：2007-09-28
摘要： A method and apparatus for varying an output clock signal frequency to match the frequency of an output data signal frequency for a SERDES circuit while maintaining a constant input clock frequency is shown. According to this method and apparatus, a PMA rate signal may control the frequency of the output clock while a datastrobe signal may be used to control the frequency of the data signal. Accordingly, the apparatus and methods may be used to produce an output data signal and a clock signal having frequencies that may be lower than the frequency of the input clock signal.
摘要翻译： 示出了用于改变输出时钟信号频率以匹配SERDES电路的输出数据信号频率的频率同时保持恒定的输入时钟频率的方法和装置。 根据该方法和装置，PMA速率信号可以控制输出时钟的频率，同时可以使用数据探测器信号来控制数据信号的频率。 因此，该装置和方法可用于产生具有可能低于输入时钟信号的频率的频率的输出数据信号和时钟信号。
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