公开(公告)号：US20080250205A1

公开(公告)日：2008-10-09

申请号：US12116676

申请日：2008-05-07

申请人： GORDON T. DAVIS ,  Richard W. Doing ,  John D. Jabusch ,  M VV A. Krishna ,  Brett Olsson ,  Eric F. Robinson ,  Sumedh W. Sathaye ,  Jeffrey R. Summers

发明人： GORDON T. DAVIS ,  Richard W. Doing ,  John D. Jabusch ,  M VV A. Krishna ,  Brett Olsson ,  Eric F. Robinson ,  Sumedh W. Sathaye ,  Jeffrey R. Summers

IPC分类号： G06F12/00 ,  G06N5/02

CPC分类号： G06F12/0864 ,  G06F12/0875 ,  G06F12/0897 ,  G06F2212/6082

摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for a single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines is provided. A mechanism is described for indexing into the cache, and selecting the desired line. Control is exercised over which lines are contained within the cache. Provision is made for selection between a trace line and a conventional line when both match during a tag compare step.

摘要翻译： 体现在用于设计，制造和/或测试用于单个统一级别的一个指令高速缓存的机器可读存储介质中的设计结构，其中一些行可以包含跟踪和相同同余类中的其他行的设计可以包含一致的指令块 提供常规的高速缓存线。 描述了一种用于索引到缓存中并选择所需行的机制。 对缓存中包含哪些行进行控制。 当在标签比较步骤中匹配时，提供在轨迹线和常规线之间的选择。