公开(公告)号：US5459843A

公开(公告)日：1995-10-17

申请号：US282412

申请日：1994-07-28

申请人： Gordon T. Davis ,  Sebastian T. Ventrone ,  John J. Reilly ,  Baiju D. Mandalia ,  Michael G. Holung ,  William R. Robinson, Jr.

发明人： Gordon T. Davis ,  Sebastian T. Ventrone ,  John J. Reilly ,  Baiju D. Mandalia ,  Michael G. Holung ,  William R. Robinson, Jr.

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3885 ,  G06F9/3851

摘要： A pipelined, RISC-type processor operated in parallel mode and its associated processing methods for separately handling instructions from multiple program instruction sets. The pipelined processor includes an instruction fetch unit, an instruction decode unit and n execution units. Each execution unit operates at substantially the same process cycle time, while the speed of operation of the instruction fetch unit and instruction decode unit is at least n times the cycle time of the execution units such that each phase of the pipeline separately processes n instructions substantially within one machine cycle. Timing and control circuitry is coupled to each of the principle elemental units for controlling the timing and sequence of operations on instructions.

摘要翻译： 以并行模式运行的流水线RISC型处理器及其相关处理方法，用于分别处理来自多个程序指令集的指令。 流水线处理器包括指令提取单元，指令解码单元和n个执行单元。 每个执行单元以基本上相同的处理周期时间操作，而指令获取单元和指令解码单元的操作速度至少为执行单元的周期时间的n倍，使得流水线的每个相分别基本上处理n个指令 在一个机器周期内。 定时和控制电路耦合到每个主要元件单元，用于控制指令上的操作的时序和顺序。