公开(公告)号：US06216254B1

公开(公告)日：2001-04-10

申请号：US09212769

申请日：1998-12-16

申请人： Michael S. Pesce ,  Kevin J. Gearhardt ,  Jonathan P. Kuppinger

发明人： Michael S. Pesce ,  Kevin J. Gearhardt ,  Jonathan P. Kuppinger

IPC分类号： G06F1750

CPC分类号： G01R31/31701

摘要： A system for designing integrated circuits that use frequency synthesizers to ensure testability. A testability circuit is added or connected to the frequency synthesizer that will receive allow the integrated circuit to operate in a system mode for normal function and in a test mode during testing. In the test mode, the testability circuit will inhibit the reset signal from initializing the integrated circuit until the frequency synthesizer has reached phase lock. The testability circuit may be implemented as a component in the frequency synthesizer cell in an ASIC design system such that anytime the frequency synthesizer is used, the integrated circuit is testable.

摘要翻译： 用于设计使用频率合成器确保可测试性的集成电路的系统。 可测试电路被添加或连接到频率合成器，接收允许集成电路在正常功能的系统模式下运行，并在测试期间在测试模式下运行。 在测试模式下，可测试电路将禁止复位信号初始化集成电路直到频率合成器达到锁相。 可测试性电路可以被实现为ASIC设计系统中的频率合成器单元中的组件，使得在使用频率合成器时，集成电路是可测试的。