公开(公告)号：US07376820B2

公开(公告)日：2008-05-20

申请号：US09741802

申请日：2000-12-22

申请人： Michihide Kimura ,  Atsuhiro Suga ,  Hideo Miyake ,  Satoshi Imai ,  Yasuki Nakamura

发明人： Michihide Kimura ,  Atsuhiro Suga ,  Hideo Miyake ,  Satoshi Imai ,  Yasuki Nakamura

IPC分类号： G06F9/44 ,  G06F9/54

CPC分类号： G06F9/3838 ,  G06F9/3836 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3861 ,  G06F9/3879

摘要： In the control section, an operation instruction not prescribing a functional specification, and a unit for processing the specific application-purpose operation instruction is provided within the processor core. The structure of this unit can be changed based on a flexible pipeline structure, and is separately designed for each application field. A register that prescribes a latency from when an instruction of the above unit is issued till when a result can be utilized is also provided in the processor core so as to prevent contention of an output port. Another register that prescribes a latency relating to a constraint of an interval of issuing an instruction of the above unit is also provided in the processor core so as to prevent contention of a resource with the preceding instructions.

摘要翻译： 在处理器核心中，在控制部分中提供不指定功能规格的操作指令和用于处理特定应用目的操作指令的单元。 该单元的结构可以基于灵活的管道结构进行更改，并为每个应用领域单独设计。 在处理器核心中还设置有从上述单元的指令发出到可以利用结果的延迟的寄存器，以防止输出端口的争用。 规定与发布上述单元的指令的间隔的约束有关的延迟的另一个寄存器也被提供在处理器核心中，以便防止具有前面指令的资源的争用。