公开(公告)号：US20070196992A1

公开(公告)日：2007-08-23

申请号：US11442009

申请日：2006-05-26

申请人： Mo Hong Xiang ,  John Chen ,  Bei Zhu ,  Dai Gao ,  Hanming Wu

发明人： Mo Hong Xiang ,  John Chen ,  Bei Zhu ,  Dai Gao ,  Hanming Wu

IPC分类号： H01L21/331 ,  H01L21/8222

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/66636 ,  H01L29/7848

摘要： A method for forming a semiconductor integrated circuit device, e.g., MOS, CMOS. The method includes providing a semiconductor substrate, e.g., silicon substrate, silicon on insulator. The method includes forming a dielectric layer (e.g., silicon dioxide, silicon nitride, silicon oxynitride) overlying the semiconductor substrate. The method also includes forming a gate layer (e.g., polysilicon) overlying the dielectric layer. The method patterns the gate layer to form a gate structure including edges. The method includes forming a dielectric layer overlying the gate structure to protect the gate structure including the edges. In a specific embodiment, sidewall spacers are formed using portions of the dielectric layer. The method etches a source region and a drain region adjacent to the gate structure using the dielectric layer as a protective layer. In a preferred embodiment, the method deposits using selective epi growth of silicon germanium material into the source region and the drain region to fill the etched source region and the etched drain region and simultaneously introduces a dopant impurity species into the silicon germanium material during a portion of the time associated with the depositing of the silicon germanium material to dope the silicon germanium material during the portion of the time associated with the depositing of the silicon germanium material. In a specific embodiment, the method also includes causing a channel region between the source region and the drain region to be strained in compressive mode from at least the silicon germanium material formed in the source region and the drain region.

摘要翻译： 一种用于形成例如MOS，CMOS的半导体集成电路器件的方法。 该方法包括提供半导体衬底，例如硅衬底，绝缘体上硅。 该方法包括形成覆盖半导体衬底的电介质层（例如，二氧化硅，氮化硅，氮氧化硅）。 该方法还包括形成覆盖在电介质层上的栅极层（例如，多晶硅）。 该方法对栅极层进行图案以形成包括边缘的栅极结构。 该方法包括形成覆盖栅极结构的电介质层，以保护包括边缘的栅极结构。 在具体实施例中，使用介电层的部分形成侧壁间隔物。 该方法使用电介质层作为保护层来蚀刻与栅极结构相邻的源极区域和漏极区域。 在优选实施例中，该方法利用硅锗材料的选择性外延生长沉积到源极区域和漏极区域中以填充蚀刻的源极区域和蚀刻的漏极区域，同时在掺杂杂质物质的一部分 在与沉积硅锗材料相关联的部分时间期间沉积硅锗材料以掺杂硅锗材料的时间。 在具体实施例中，该方法还包括使源区域和漏区域之间的沟道区域至少在形成于源极区域和漏极区域中的硅锗材料以压缩模式应变。