Method and apparatus for calibration of successive approximation register analog-to-digital converters
    1.
    发明授权
    Method and apparatus for calibration of successive approximation register analog-to-digital converters 有权
    用于校准逐次逼近寄存器模数转换器的方法和装置

    公开(公告)号:US09041569B2

    公开(公告)日:2015-05-26

    申请号:US13931767

    申请日:2013-06-28

    IPC分类号: H03M1/06

    摘要: A successive approximation register (SAR) ADC includes an SAR comparator circuit including first and second inputs, a control input, and first and second outputs. The SAR comparator circuit further includes a plurality of capacitors coupled to the first and second inputs and includes a plurality of switches configured to couple the plurality of capacitors to one of a first voltage and a second voltage. The SAR ADC further includes a calibration circuit coupled to the first and second outputs and to the control input of the SAR comparator. The calibration circuit is configured to control the plurality of switches to selectively couple the plurality of capacitors to one of the first and second voltages to provide a calibration signal to the SAR comparator circuit. The calibration circuit is configured to calibrate the SAR comparator based on corresponding output signals at the first and second outputs.

    摘要翻译: 逐次逼近寄存器(SAR)ADC包括包括第一和第二输入,控制输入以及第一和第二输出的SAR比较器电路。 SAR比较器电路还包括耦合到第一和第二输入的多个电容器,并且包括被配置为将多个电容器耦合到第一电压和第二电压中的一个的多个开关。 SAR ADC还包括耦合到第一和第二输出和SAR比较器的控制输入的校准电路。 校准电路被配置为控制多个开关以选择性地将多个电容器耦合到第一和第二电压之一,以向SAR比较器电路提供校准信号。 校准电路被配置为基于在第一和第二输出处的相应输出信号校准SAR比较器。

    Clocked Reference Buffer in a Successive Approximation Analog-to-Digital Converter
    2.
    发明申请
    Clocked Reference Buffer in a Successive Approximation Analog-to-Digital Converter 有权
    连续近似模数转换器中的时钟参考缓冲器

    公开(公告)号:US20140333465A1

    公开(公告)日:2014-11-13

    申请号:US13892235

    申请日:2013-05-10

    IPC分类号: H03M1/12

    CPC分类号: H03M1/0845 H03M1/466

    摘要: A voltage reference circuit includes a capacitor including a first terminal and including a second terminal coupled to a power supply node. The voltage reference circuit further includes an amplifier, a first transistor, and a switch. The amplifier includes a first input configured to receive a reference voltage input signal, a second input configured to receive a feedback signal, and an output. The first transistor includes a source coupled to the second input of the amplifier and to an output node, a gate coupled to the capacitor, and a drain. The first transistor is configured to provide a reference voltage at the source based on a charge provided to the gate by the capacitor. The switch includes a first terminal coupled to the output of the amplifier, and includes a second terminal coupled to the first terminal of the capacitor.

    摘要翻译: 电压参考电路包括包括第一端子并且包括耦合到电源节点的第二端子的电容器。 电压参考电路还包括放大器,第一晶体管和开关。 放大器包括被配置为接收参考电压输入信号的第一输入,被配置为接收反馈信号的第二输入和输出。 第一晶体管包括耦合到放大器的第二输入端和输出节点的源极,耦合到电容器的栅极和漏极。 第一晶体管被配置为基于由电容器提供给栅极的电荷在源极处提供参考电压。 开关包括耦合到放大器的输出的第一端子,并且包括耦合到电容器的第一端子的第二端子。

    Clocked reference buffer in a successive approximation analog-to-digital converter
    3.
    发明授权
    Clocked reference buffer in a successive approximation analog-to-digital converter 有权
    逐次逼近模数转换器中的时钟参考缓冲器

    公开(公告)号:US08922418B2

    公开(公告)日:2014-12-30

    申请号:US13892235

    申请日:2013-05-10

    IPC分类号: H03M1/12

    CPC分类号: H03M1/0845 H03M1/466

    摘要: A voltage reference circuit includes a capacitor including a first terminal and including a second terminal coupled to a power supply node. The voltage reference circuit further includes an amplifier, a first transistor, and a switch. The amplifier includes a first input configured to receive a reference voltage input signal, a second input configured to receive a feedback signal, and an output. The first transistor includes a source coupled to the second input of the amplifier and to an output node, a gate coupled to the capacitor, and a drain. The first transistor is configured to provide a reference voltage at the source based on a charge provided to the gate by the capacitor. The switch includes a first terminal coupled to the output of the amplifier, and includes a second terminal coupled to the first terminal of the capacitor.

    摘要翻译: 电压参考电路包括包括第一端子并且包括耦合到电源节点的第二端子的电容器。 电压参考电路还包括放大器,第一晶体管和开关。 放大器包括被配置为接收参考电压输入信号的第一输入,被配置为接收反馈信号的第二输入和输出。 第一晶体管包括耦合到放大器的第二输入端和输出节点的源极,耦合到电容器的栅极和漏极。 第一晶体管被配置为基于由电容器提供给栅极的电荷在源极处提供参考电压。 开关包括耦合到放大器的输出的第一端子,并且包括耦合到电容器的第一端子的第二端子。

    Method and Apparatus for Calibration of Successive Approximation Register Analog-to-Digital Converters
    4.
    发明申请
    Method and Apparatus for Calibration of Successive Approximation Register Analog-to-Digital Converters 有权
    用于校正连续近似寄存器模数转换器的方法和装置

    公开(公告)号:US20150002321A1

    公开(公告)日:2015-01-01

    申请号:US13931767

    申请日:2013-06-28

    IPC分类号: H03M1/06

    摘要: A successive approximation register (SAR) ADC includes an SAR comparator circuit including first and second inputs, a control input, and first and second outputs. The SAR comparator circuit further includes a plurality of capacitors coupled to the first and second inputs and includes a plurality of switches configured to couple the plurality of capacitors to one of a first voltage and a second voltage. The SAR ADC further includes a calibration circuit coupled to the first and second outputs and to the control input of the SAR comparator. The calibration circuit is configured to control the plurality of switches to selectively couple the plurality of capacitors to one of the first and second voltages to provide a calibration signal to the SAR comparator circuit. The calibration circuit is configured to calibrate the SAR comparator based on corresponding output signals at the first and second outputs.

    摘要翻译: 逐次逼近寄存器(SAR)ADC包括包括第一和第二输入,控制输入以及第一和第二输出的SAR比较器电路。 SAR比较器电路还包括耦合到第一和第二输入的多个电容器,并且包括被配置为将多个电容器耦合到第一电压和第二电压之一的多个开关。 SAR ADC还包括耦合到第一和第二输出和SAR比较器的控制输入的校准电路。 校准电路被配置为控制多个开关以选择性地将多个电容器耦合到第一和第二电压之一,以向SAR比较器电路提供校准信号。 校准电路被配置为基于在第一和第二输出处的相应输出信号校准SAR比较器。