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公开(公告)号：US06983436B2
公开(公告)日：2006-01-03
申请号：US10690651
申请日：2003-10-23
申请人： Naoki Amekawa
发明人： Naoki Amekawa
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5045
摘要： In a semiconductor integrated circuit, there is provided a method for correcting crosstalk, which exerts an influence via coupling capacitance between wiring by the signal transitions between adjacent wiring, comprising the step of creating a candidate for buffer division, the step of creating a candidate for cell movement, or the step of victim net logic synthesis. Thereby, the crosstalk is corrected through the buffer division, the cell movement, or an increase of elements in number by logic decomposition, logic inversion and a change of fan-outs in number.
摘要翻译： 在半导体集成电路中，提供了一种用于校正串扰的方法，其通过相邻布线之间的信号转换在布线之间通过耦合电容施加影响，包括创建用于缓冲区划分的候选的步骤，创建候选者的步骤 细胞运动或受害者网络逻辑综合的步骤。 由此，通过缓冲器分割，单元移动或通过逻辑分解，逻辑反转和扇出数的改变来增加元件的数量来纠正串扰。
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2.发明申请Delay calculation method, timing analysis method, calculation object network approximation method, and delay control method 审中-公开延迟计算方法，时序分析法，计算对象网络近似法，延迟控制法等公开(公告)号：US20050256921A1
公开(公告)日：2005-11-17
申请号：US10891496
申请日：2004-07-15
CPC分类号： G06F17/5036
摘要： A delay calculation method considering a net adjacent to a delay calculation object net of a semiconductor integrated circuit includes: an adjacent net internal resistance selecting step of selecting a combination of static state of an adjacent net driving cell; a coupling capacitance grounding step of multiplying a coupling capacitance by a coefficient obtained from an internal resistance of the adjacent net driving cell selected by the adjacent net internal resistance selecting step, and the like, and grounding the value obtained thereby as the coupling capacitance of the delay calculating object net; and a delay value deriving step of deriving the delay value from a circuit obtained by these steps. A problem of the delay calculation method that an accurate delay value cannot be obtained because in actuality, the adjacent wire whose potential fluctuates is approximated to zero potential is solved by this structure.
摘要翻译： 考虑与半导体集成电路的延迟计算对象网相邻的网络的延迟计算方法包括：相邻的网络内部电阻选择步骤，选择相邻网络驱动单元的静态的组合; 耦合电容接地步骤，将耦合电容乘以由相邻的净内部电阻选择步骤选择的相邻净驱动单元的内部电阻获得的系数等，并将由此获得的值接地作为 延迟计算物体网; 以及延迟值导出步骤，从通过这些步骤获得的电路导出延迟值。 通过这种结构解决了实际上电位波动近似为零电位的相邻导线的滞后计算方法不能获得精确延迟值的问题。
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3.发明申请DELAY LIBRARY, DELAY LIBRARY CREATION METHOD, AND DELAY CALCULATION METHOD 审中-公开延迟图书馆，延迟图书馆创作方法和延迟计算方法公开(公告)号：US20100313176A1
公开(公告)日：2010-12-09
申请号：US12743965
申请日：2009-02-24
IPC分类号： G06F9/455
CPC分类号： G06F17/5031
摘要： A timing window (TW) representing a time zone where a signal transition possibly occurs in a time axis is generated for each of input signals in input terminals in a multi-input logic cell based on a signal transition timing in each of the input terminals. An overlap between the timing windows (TW) of input signals is detected, and a circuit delay time is calculated by selectively using one of a synchronous transition time and an asynchronous transition time in accordance with the overlap between the timing windows (TW). These processing steps are sequentially repeated to eliminate an optimistic or pessimistic analysis in the calculation of delay times in the multi-input logic cell.
摘要翻译： 基于每个输入端子中的信号转换时序，为多输入逻辑单元中的输入端子中的每个输入信号产生表示在时间轴中可能发生信号转换的时区的定时窗口（TW）。 检测输入信号的定时窗口（TW）之间的重叠，并且通过根据时序窗口（TW）之间的重叠选择性地使用同步转换时间和异步转换时间之一来计算电路延迟时间。 顺序地重复这些处理步骤，以消除在多输入逻辑单元中的延迟时间的计算中的乐观或悲观的分析。
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4.发明授权公开(公告)号：US07225418B2
公开(公告)日：2007-05-29
申请号：US10863231
申请日：2004-06-09
申请人： Kenji Shimazaki , Kazuhiro Sato , Takahiro Ichinomiya , Nobufusa Iwanishi , Naoki Amekawa , Masaaki Hirata , Shouzou Hirano
发明人： Kenji Shimazaki , Kazuhiro Sato , Takahiro Ichinomiya , Nobufusa Iwanishi , Naoki Amekawa , Masaaki Hirata , Shouzou Hirano
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G01R31/318357 , G01R31/31928
摘要： There are contained the step of forming voltage waveform information by calculating a voltage waveform of each instance of a semiconductor integrated circuit at a power-supply terminal based on circuit information and analyzing the voltage waveform of each instance, the step of forming voltage abstraction information by abstracting the voltage waveform information, and the step of calculating a delay value of the instance based on the voltage abstraction information.
摘要翻译： 包含通过基于电路信息计算电源端子处的半导体集成电路的每个实例的电压波形并分析各实例的电压波形来形成电压波形信息的步骤，通过以下步骤形成电压抽象信息： 抽取电压波形信息，以及基于电压抽象信息计算实例的延迟值的步骤。
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公开(公告)号：US07231622B2
公开(公告)日：2007-06-12
申请号：US11226326
申请日：2005-09-15
申请人： Naoki Amekawa
发明人： Naoki Amekawa
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5045
摘要： In a semiconductor integrated circuit, there is provided a method for correcting crosstalk, which exerts an influence via coupling capacitance between wiring by the signal transitions between adjacent wiring, comprising the step of creating a candidate for buffer division, the step of creating a candidate for cell movement, or the step of victim net logic synthesis. Thereby, the crosstalk is corrected through the buffer division, the cell movement, or an increase of elements in number by logic decomposition, logic inversion and a change of fan-outs in number.
摘要翻译： 在半导体集成电路中，提供了一种用于校正串扰的方法，其通过相邻布线之间的信号转换在布线之间通过耦合电容施加影响，包括创建用于缓冲区划分的候选的步骤，创建候选者的步骤 细胞运动或受害者网络逻辑综合的步骤。 由此，通过缓冲器分割，单元移动或通过逻辑分解，逻辑反转和扇出数的改变来增加元件的数量来纠正串扰。
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公开(公告)号：US20060015834A1
公开(公告)日：2006-01-19
申请号：US11226326
申请日：2005-09-15
申请人： Naoki Amekawa
发明人： Naoki Amekawa
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5045
摘要： In a semiconductor integrated circuit, there is provided a method for correcting crosstalk, which exerts an influence via coupling capacitance between wiring by the signal transitions between adjacent wiring, comprising the step of creating a candidate for buffer division, the step of creating a candidate for cell movement, or the step of victim net logic synthesis. Thereby, the crosstalk is corrected through the buffer division, the cell movement, or an increase of elements in number by logic decomposition, logic inversion and a change of fan-outs in number.
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7.发明申请Method for characterizing cells with consideration for bumped waveform and delay time calculation method for semiconductor integrated circuits using the same 审中-公开考虑使用其的半导体集成电路的凸起波形和延迟时间计算方法来表征单元的方法公开(公告)号：US20050232066A1
公开(公告)日：2005-10-20
申请号：US11108696
申请日：2005-04-19
CPC分类号： G06F17/5036
摘要： An effective input terminal capacitance which is effectively equivalent to a cell in which a waveform distortion is caused due to the Miller effect and a drive load connected to the cell is calculated in advance, and the cell and the drive load are replaced by the calculated effective input terminal capacitance, while considering that the Miller effect is caused according to the size of the drive load driven by a delay time calculation subject circuit, such as a cell, or the like, and a distortion occurs in input and output waveforms of the delay time calculation subject circuit due to the Miller effect. Thereafter, a circuit simulation is carried out using the effective input terminal capacitance. A resultant effective input terminal capacitance value is characterized as a function of an input slope waveform and the drive load and converted to table data.
摘要翻译： 预先计算有效输入端子电容，其有效地等效于由于米勒效应引起的波形失真的单元和连接到单元的驱动负载的单元，并且计算单元和驱动负载被计算的有效 输入端子电容，同时考虑到由延迟时间计算对象电路（例如单元等）驱动的驱动负载的大小引起米勒效应，并且在延迟的输入和输出波形中发生失真 时间计算主题电路由于米勒效应。 此后，使用有效输入端子电容进行电路仿真。 合成的有效输入端电容值的特征在于输入斜率波形和驱动负载的函数，并转换为表数据。
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