摘要:
A computer system includes a central processor unit (“CPU”), a dynamic random access memory (“DRAM”) device, a key storage device storing a decryption key, a decryption engine and a system controller coupling the CPU to the DRAM. All of these components are fabricated on a common integrated circuit substrate so that interconnections between these components are protected from unauthorized access. The system controller is also coupled through to a non-volatile memory that stores a computer program that has been encrypted. In operation, the computer program is transferred through the system controller to the decryption engine, which uses the decryption key to decrypt the computer program. The CPU executes the encrypted program, and, in doing so, transfers data between the CPU and the system memory. This data is protected from unauthorized access because the connections between the CPU and the system memory are internal to the integrated circuit.
摘要:
An imaging system may include an array of image pixels. The array of image pixels may be provided with one or more rows and columns of optically shielded dark image pixels. The dark image pixels may be used to produce verification image data that follows the same pixel-to-output data path of light-receiving pixels. The output signals from dark pixels may be continuously or intermittently compared with a set of expected output signals to verify that the imaging system is functioning properly. In some arrangements, verification image data may include a current frame number that is encoded into the dark pixels. The encoded current frame number may be compared with an expected current frame number. In other arrangements, dark pixels may be configured to have a predetermined pattern of conversion gain levels. The output signals may be compared with a “golden” image or other predetermined set of expected output signals.
摘要:
This is generally directed to systems and methods for control of two or more devices through a shared control bus. For example, the devices can be coupled to a host system through the control bus. In some embodiments, the devices can be configured by the host system through address select pins of the devices. For example, the host system can sequentially program each device to change its default address to a unique address. In some embodiments, an event can be propagated through each device, thus resulting in each device receiving the event at a different time. In some embodiments, configuration by the host system can include programming each device with a value representing its own position in the chain. In this case, a device can use this value to delay its response to the event, thereby allowing all the devices in the chain to respond to the event simultaneously.
摘要:
A variable rate image sensor outputs pixel data at a variable rate using lookup tables to selectively read out particular rows at particular times. The readout rate is not constant, allowing for a smaller image buffer in the overall system.
摘要:
A pipelined computer processor is presented that reduces data hazards such that high processor utilization is attained. The processor restructures a set of instructions to operate concurrently on multiple pieces of data in multiple passes. One subset of instructions operates on one piece of data while different subsets of instructions operate concurrently on different pieces of data. A validity pipeline tracks the priming and draining of the pipeline processor to ensure that only valid data is written to registers or memory. Pass-dependent addressing is provided to correctly address registers and memory for different pieces of data.
摘要:
An imaging system may include an array of image pixels. The array of image pixels may be provided with one or more rows and columns of optically shielded dark image pixels. The dark image pixels may be used to produce verification image data that follows the same pixel-to-output data path of light-receiving pixels. The output signals from dark pixels may be continuously or intermittently compared with a set of expected output signals to verify that the imaging system is functioning properly. In some arrangements, verification image data may include a current frame number that is encoded into the dark pixels. The encoded current frame number may be compared with an expected current frame number. In other arrangements, dark pixels may be configured to have a predetermined pattern of conversion gain levels. The output signals may be compared with a “golden” image or other predetermined set of expected output signals.
摘要:
This is generally directed to systems and methods for control of two or more devices through a shared control bus. For example, the devices can be coupled to a host system through the control bus. In some embodiments, the devices can be configured by the host system through address select pins of the devices. For example, the host system can sequentially program each device to change its default address to a unique address. In some embodiments, an event can be propagated through each device, thus resulting in each device receiving the event at a different time. In some embodiments, configuration by the host system can include programming each device with a value representing its own position in the chain. In this case, a device can use this value to delay its response to the event, thereby allowing all the devices in the chain to respond to the event simultaneously.
摘要:
An Electronic device may include a master camera module, a slave camera module, and host subsystems. The master camera module may control some of the operations of the slave camera module. The master camera module may transmit data to the slave camera module. The master camera module may interrupt data transmission to the slave camera module, when a delay-sensitive event occurs, to transmit information corresponding to the delay-sensitive event. The slave camera module may respond to the event information with a predetermined fixed delay relative to the occurrence of the event at the master camera module.
摘要:
An Electronic device may include a master camera module, a slave camera module, and host subsystems. The master camera module may control some of the operations of the slave camera module. The master camera module may transmit data to the slave camera module. The master camera module may interrupt data transmission to the slave camera module, when a delay-sensitive event occurs, to transmit information corresponding to the delay-sensitive event. The slave camera module may respond to the event information with a predetermined fixed delay relative to the occurrence of the event at the master camera module.
摘要:
A variable rate image sensor outputs pixel data at a variable rate using lookup tables to selectively read out particular rows at particular times. The readout rate is not constant, allowing for a smaller image buffer in the overall system.