公开(公告)号：US09219065B2

公开(公告)日：2015-12-22

申请号：US12573589

申请日：2009-10-05

申请人： Eugene A. Fitzgerald ,  Nicole Gerrish

发明人： Eugene A. Fitzgerald ,  Nicole Gerrish

IPC分类号： H01L29/72 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/10

CPC分类号： H01L27/0922 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/1054

摘要： A method of fabricating a circuit comprising an nMOSFET includes providing a substrate, depositing a strain-inducing material comprising germanium over the substrate, and integrating a pMOSFET on the substrate, the pMOSFET comprising a strained channel having a surface roughness of less than 1 nm. The strain-inducing material is proximate to and in contact with the pMOSFET channel, the strain in the pMOSFET channel is induced by the strain-inducing material, and a source and a drain of the pMOSFET are at least partially formed in the strain-inducing material.

摘要翻译： 制造包括nMOSFET的电路的方法包括提供衬底，在衬底上沉积包含锗的应变诱导材料，以及在衬底上集成pMOSFET，pMOSFET包括表面粗糙度小于1nm的应变通道。 应变诱导材料接近并与pMOSFET通道接触，pMOSFET通道中的应变由应变诱导材料诱导，并且pMOSFET的源极和漏极在应变诱导中至少部分地形成 材料。

公开(公告)号：US20060275972A1

公开(公告)日：2006-12-07

申请号：US11431186

申请日：2006-05-10

申请人： Eugene Fitzgerald ,  Nicole Gerrish

发明人： Eugene Fitzgerald ,  Nicole Gerrish

IPC分类号： H01L21/8238

CPC分类号： H01L27/0922 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/1054

摘要： A method of fabricating a CMOS inverter including providing a heterostructure having a Si substrate, a relaxed Si1-xGex layer on the Si substrate, and a strained surface layer on said relaxed Si1-xGex layer; and integrating a pMOSFET and an nMOSFET in said heterostructure, wherein the channel of said pMOSFET and the channel of the nMOSFET are formed in the strained surface layer. Another embodiment provides a method of fabricating an integrated circuit including providing a heterostructure having a Si substrate, a relaxed Si1-xGex layer on the Si substrate, and a strained layer on the relaxed Si1-xGex layer; and forming a p transistor and an n transistor in the heterostructure, wherein the strained layer comprises the channel of the n transistor and the p transistor, and the n transistor and the p transistor interconnected in a CMOS circuit.

摘要翻译： 一种制造CMOS反相器的方法，包括提供在Si衬底上具有Si衬底，弛豫的Si 1-x Ge 2 x层的异质结构，以及在Si衬底上的应变表面层 所述松弛的Si 1-x Ge x层; 以及将pMOSFET和nMOSFET集成在所述异质结构中，其中所述pMOSFET的沟道和nMOSFET的沟道形成在应变表面层中。 另一个实施例提供一种制造集成电路的方法，该集成电路包括提供在Si衬底上具有Si衬底，弛豫的Si 1-x N x Ge x Si层的异质结构和应变 层在松弛的Si 1-x Ge层上; 以及在所述异质结构中形成p晶体管和n晶体管，其中所述应变层包括所述n晶体管和所述p晶体管的沟道，并且所述n晶体管和所述p晶体管在CMOS电路中互连。

公开(公告)号：US20050106850A1

公开(公告)日：2005-05-19

申请号：US10953260

申请日：2004-09-29

申请人： Eugene Fitzgerald ,  Nicole Gerrish

发明人： Eugene Fitzgerald ,  Nicole Gerrish

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L27/108

CPC分类号： H01L27/0922 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/1054

摘要： A method of fabricating a CMOS inverter including providing a heterostructure having a Si substrate, a relaxed Si1-xGex layer on the Si substrate, and a strained surface layer on said relaxed Si1-xGex layer; and integrating a pMOSFET and an nMOSFET in said heterostructure, wherein the channel of said pMOSFET and the channel of the nMOSFET are formed in the strained surface layer. Another embodiment provides a method of fabricating an integrated circuit including providing a heterostructure having a Si substrate, a relaxed Si1-xGex layer on the Si substrate, and a strained layer on the relaxed Si1-xGex layer; and forming a p transistor and an n transistor in the heterostructure, wherein the strained layer comprises the channel of the n transistor and the p transistor, and the n transistor and the p transistor are interconnected in a CMOS circuit.

摘要翻译： 一种制造CMOS反相器的方法，包括提供在Si衬底上具有Si衬底，弛豫的Si 1-x Ge 2 x层的异质结构，以及在Si衬底上的应变表面层 所述松弛的Si 1-x Ge x层; 以及将pMOSFET和nMOSFET集成在所述异质结构中，其中所述pMOSFET的沟道和nMOSFET的沟道形成在应变表面层中。 另一个实施例提供一种制造集成电路的方法，该集成电路包括提供在Si衬底上具有Si衬底，弛豫的Si 1-x N x Ge x Si层的异质结构和应变 层在松弛的Si 1-x Ge层上; 以及在所述异质结构中形成p晶体管和n晶体管，其中所述应变层包括所述n晶体管和所述p晶体管的沟道，并且所述n晶体管和所述p晶体管在CMOS电路中互连。

公开(公告)号：US06881632B2

公开(公告)日：2005-04-19

申请号：US10611739

申请日：2003-07-01

申请人： Eugene A. Fitzgerald ,  Nicole Gerrish

发明人： Eugene A. Fitzgerald ,  Nicole Gerrish

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L21/336

CPC分类号： H01L27/0922 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/1054

摘要： A method of fabricating a CMOS inverter including providing a heterostructure having a Si substrate, a relaxed Si1-xGex layer on the Si substrate, and a strained surface layer on said relaxed Si1-xGex layer; and integrating a pMOSFET and an nMOSFET in said heterostructure, wherein the channel of said pMOSFET and the channel of the nMOSFET are formed in the strained surface layer. Another embodiment provides a method of fabricating an integrated circuit including providing a heterostructure having a Si substrate, a relaxed Si1-xGex layer on the Si substrate, and a strained layer on the relaxed Si1-xGex layer; and forming a p transistor and an n transistor in the heterostructure, wherein the strained layer comprises the channel of the n transistor and the p transistor, and the n transistor and the p transistor are interconnected in a CMOS circuit.

摘要翻译： 一种制造CMOS反相器的方法，包括提供在Si衬底上具有Si衬底，弛豫的Si 1-x Ge 2 x层的异质结构，以及在Si衬底上的应变表面层 所述松弛的Si 1-x Ge x层; 以及将pMOSFET和nMOSFET集成在所述异质结构中，其中所述pMOSFET的沟道和nMOSFET的沟道形成在应变表面层中。 另一个实施例提供一种制造集成电路的方法，该集成电路包括提供在Si衬底上具有Si衬底，弛豫的Si 1-x N x Ge x Si层的异质结构和应变 层在松弛的Si 1-x Ge层上; 以及在所述异质结构中形成p晶体管和n晶体管，其中所述应变层包括所述n晶体管和所述p晶体管的沟道，并且所述n晶体管和所述p晶体管在CMOS电路中互连。

公开(公告)号：US06649480B2

公开(公告)日：2003-11-18

申请号：US09884172

申请日：2001-06-19

申请人： Eugene A. Fitzgerald ,  Nicole Gerrish

发明人： Eugene A. Fitzgerald ,  Nicole Gerrish

IPC分类号： H01L21336

CPC分类号： H01L27/0922 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/1054

摘要： A method of fabricating a CMOS inverter including providing a heterostructure having a Si substrate, a relaxed Si1-x Gex layer on the Si substrate, and a strained surface layer on said relaxed Si1-x Gex layer; and integrating a pMOSFET and an nMOSFET in said heterostructure, wherein the channel of said pMOSFET and the channel of the nMOSFET are formed in the strained surface layer. Another embodiment provides a method of fabricating an integrated circuit including providing a heterostructure having a Si substrate, a relaxed Si1-xGex layer on the Si substrate, and a strained layer on the relaxed Si1-x Gex layer; and forming a p transistor and an n transistor in the heterostructure, wherein the strained layer comprises the channel of the n transistor and the p transistor, and the n transistor and the p transistor are interconnected in a CMOS circuit.

摘要翻译： 一种制造CMOS反相器的方法，包括提供具有Si衬底的异质结构，Si衬底上的弛豫Si1-xGex层以及所述弛豫Si1-xGex层上的应变表面层; 以及将pMOSFET和nMOSFET集成在所述异质结构中，其中所述pMOSFET的沟道和nMOSFET的沟道形成在应变表面层中。 另一实施例提供一种制造集成电路的方法，包括提供具有Si衬底，Si衬底上的弛豫Si1-xGex层的异质结构和弛豫Si1-xGex层上的应变层; 以及在所述异质结构中形成p晶体管和n晶体管，其中所述应变层包括所述n晶体管和所述p晶体管的沟道，并且所述n晶体管和所述p晶体管在CMOS电路中互连。