公开(公告)号：US07027350B2

公开(公告)日：2006-04-11

申请号：US10474260

申请日：2002-03-22

Applicant: Pascal Narche

Inventor： Pascal Narche

IPC: G11C11/00

CPC classification number: G11C16/22

Abstract: A device for read protection of at least one area of a non-volatile memory includes an address decoder outputting an addressing signal on one of its output terminals when an the address corresponds to one of the read protected areas of the memory. A state memory is provided for each read protected area to output a state signal indicating whether or not the area is protected in read. A program instructions decoder outputs a program signal indicating whether or not the current addressing operation corresponds to a program instruction. A logic circuit responsive to the addressing signal, the state signal and the program signal outputs an instruction signal to read the read protected area when the program signal indicates that the current addressing operation is applicable to a program instruction.

Abstract translation: 用于对非易失性存储器的至少一个区域进行读保护的装置包括地址解码器，当地址对应于存储器的读取保护区域之一时，地址解码器在其输出端子之一上输出寻址信号。 为每个读取保护区域提供状态存储器，以输出指示区域是否被保护读取的状态信号。 程序指令解码器输出指示当前寻址操作是否对应于程序指令的程序信号。 响应于寻址信号的逻辑电路，状态信号和程序信号，当程序信号指示当前寻址操作适用于程序指令时，输出指令信号以读取读保护区。

公开(公告)号：US07043628B2

公开(公告)日：2006-05-09

申请号：US09995251

申请日：2001-11-27

Applicant: Franck Roche ,  Pascal Narche ,  Ludovic Ruat

Inventor： Franck Roche ,  Pascal Narche ,  Ludovic Ruat

IPC: G06F9/00

CPC classification number: G06F11/2273 ,  G01R31/31701 ,  G01R31/31719

Abstract: A microprocessor includes a counter having a counting input and a reset input. The counting input is coupled to a first terminal of the microprocessor for the selection of an operating mode thereof by application of a predetermined number of pulses to the first terminal. The reset input of the counter is driven by a control signal present on a second terminal of the microprocessor. The control signal is maintained by default at a first logic value ensuring the maintaining at zero of the counter during the initialization period by a circuit internal or external the microprocessor. Immunity against electromagnetic perturbations causing the microprocessor to enter into the test mode is provided.

Abstract translation: 微处理器包括具有计数输入和复位输入的计数器。 计数输入耦合到微处理器的第一端，用于通过向第一终端施加预定数量的脉冲来选择其操作模式。 计数器的复位输入由存在于微处理器的第二端子上的控制信号驱动。 控制信号默认维持在第一逻辑值，确保在初始化期间通过内部或外部微处理器的电路将计数器保持在零。 提供了防止导致微处理器进入测试模式的电磁扰动的抗扰度。