公开(公告)号：US20080066134A1

公开(公告)日：2008-03-13

申请号：US11467755

申请日：2006-08-28

申请人： Paul Wiercienski ,  Chris Wiesner ,  Oswin Hall

发明人： Paul Wiercienski ,  Chris Wiesner ,  Oswin Hall

IPC分类号： H04N7/173 ,  H04N7/16

CPC分类号： H04N19/59 ,  H04N19/427 ,  H04N19/428 ,  H04N19/44

摘要： A system for processing video information, the system including a memory configured to store video information, a memory controller coupled to the memory and configured to receive memory requests for the video information, a first video signal processing client coupled to the memory controller. The first video signal processing client including a video signal processor, a buffer coupled to the video signal processor, and a memory request module coupled to the memory controller and to the buffer, the memory request module being configured to submit amortized memory requests to the memory controller.

摘要翻译： 一种用于处理视频信息的系统，所述系统包括被配置为存储视频信息的存储器，耦合到所述存储器并被配置为接收对所述视频信息的存储器请求的存储器控​​制器，耦合到所述存储器控制器的第一视频信号处理客户端。 第一视频信号处理客户机包括视频信号处理器，耦合到视频信号处理器的缓冲器以及耦合到存储器控制器和缓冲器的存储器请求模块，该存储器请求模块被配置为向存储器提交摊销的存储器请求 控制器。

公开(公告)号：US07969512B2

公开(公告)日：2011-06-28

申请号：US11467755

申请日：2006-08-28

申请人： Paul Wiercienski ,  Chris Wiesner ,  Oswin Hall

发明人： Paul Wiercienski ,  Chris Wiesner ,  Oswin Hall

IPC分类号： H04N9/64

CPC分类号： H04N19/59 ,  H04N19/427 ,  H04N19/428 ,  H04N19/44

摘要： A system for processing video information, the system including a memory configured to store video information, a memory controller coupled to the memory and configured to receive memory requests for the video information, a first video signal processing client coupled to the memory controller. The first video signal processing client including a video signal processor, a buffer coupled to the video signal processor, and a memory request module coupled to the memory controller and to the buffer, the memory request module being configured to submit amortized memory requests to the memory controller.

摘要翻译： 一种用于处理视频信息的系统，所述系统包括被配置为存储视频信息的存储器，耦合到所述存储器并被配置为接收对所述视频信息的存储器请求的存储器控​​制器，耦合到所述存储器控制器的第一视频信号处理客户端。 第一视频信号处理客户机包括视频信号处理器，耦合到视频信号处理器的缓冲器以及耦合到存储器控制器和缓冲器的存储器请求模块，该存储器请求模块被配置为向存储器提交摊销的存储器请求 控制器。

公开(公告)号：US20110109794A1

公开(公告)日：2011-05-12

申请号：US12614234

申请日：2009-11-06

申请人： Paul Wiercienski ,  Yunwei Jia

发明人： Paul Wiercienski ,  Yunwei Jia

IPC分类号： H04N7/01

CPC分类号： H04N7/0117 ,  G06T3/4053

摘要： Presented herein are caching structures and apparatus for use in block based video. In one embodiment, there is described a system for providing receiving lower resolution frames and generating higher resolution frames. The system comprises an integrated circuit. The integrated circuit comprises a first circuit, a direct memory access, and a cache. The first circuit maps frames that are proximate to a particular frame to the particular frame. The direct memory access fetches blocks from said proximate frames. The cache stores at least some of the blocks from said proximate frames.

摘要翻译： 这里提出的是用于基于块视频的缓存结构和装置。 在一个实施例中，描述了一种用于提供接收较低分辨率帧并生成较高分辨率帧的系统。 该系统包括集成电路。 集成电路包括第一电路，直接存储器访问和高速缓存。 第一个电路将与特定帧相邻的帧映射到特定帧。 直接存储器访问从所述邻近帧获取块。 高速缓存存储来自所述邻近帧的至少一些块。

公开(公告)号：US09449367B2

公开(公告)日：2016-09-20

申请号：US12635550

申请日：2009-12-10

申请人： Yunwei Jia ,  Paul Wiercienski

发明人： Yunwei Jia ,  Paul Wiercienski

IPC分类号： H04N7/01 ,  H04N11/20 ,  G06T3/40

CPC分类号： G06T3/4053 ,  H04N7/0117

摘要： Presented herein are caching structures and apparatus for use in block based video. In one embodiment, there is described a system receiving lower resolution frames and generating higher resolution frames. The system comprises an upsampling circuit, a first circuit, and a second circuit. The upsampling circuit upsamples a particular lower resolution frame, thereby resulting in an upsampled frame. The first circuit maps frames that are proximate to the particular frame, to the particular frame. The second circuit simultaneously updates the upsampled frame with two or more blocks from at least one of the frames that are proximate to the particular frame.

摘要翻译： 这里提出的是用于基于块视频的缓存结构和装置。 在一个实施例中，描述了接收较低分辨率帧并产生较高分辨率帧的系统。 该系统包括上采样电路，第一电路和第二电路。 上采样电路对特定的较低分辨率帧进行上采样，从而导致上采样帧。 第一个电路将接近特定帧的帧映射到特定帧。 第二电路同时使用两个或多个来自接近该特定帧的帧中的至少一个来更新上采样帧。

公开(公告)号：US20110141348A1

公开(公告)日：2011-06-16

申请号：US12635550

申请日：2009-12-10

申请人： Yunwei Jia ,  Paul Wiercienski

发明人： Yunwei Jia ,  Paul Wiercienski

IPC分类号： H04N7/01

CPC分类号： G06T3/4053 ,  H04N7/0117

摘要： Presented herein are caching structures and apparatus for use in block based video. In one embodiment, there is described a system receiving lower resolution frames and generating higher resolution frames. The system comprises an upsampling circuit, a first circuit, and a second circuit. The upsampling circuit upsamples a particular lower resolution frame, thereby resulting in an upsampled frame. The first circuit maps frames that are proximate to the particular frame, to the particular frame. The second circuit simultaneously updates the upsampled frame with two or more blocks from at least one of the frames that are proximate to the particular frame.

摘要翻译： 这里提出的是用于基于块视频的缓存结构和装置。 在一个实施例中，描述了接收较低分辨率帧并产生较高分辨率帧的系统。 该系统包括上采样电路，第一电路和第二电路。 上采样电路对特定的较低分辨率帧进行上采样，从而导致上采样帧。 第一个电路将接近特定帧的帧映射到特定帧。 第二电路同时使用两个或多个来自接近该特定帧的帧中的至少一个来更新上采样帧。