公开(公告)号：US4914634A

公开(公告)日：1990-04-03

申请号：US284038

申请日：1988-12-14

申请人： Chekib Akrout ,  Pierre Coppens ,  Bernard Denis ,  Pierre-Yves Urena

发明人： Chekib Akrout ,  Pierre Coppens ,  Bernard Denis ,  Pierre-Yves Urena

IPC分类号： G11C11/407 ,  G11C11/402 ,  G11C11/419

CPC分类号： G11C11/419

摘要： A semiconductor memory device including a pair of bit lines (BL, BL) having relatively high stray capacitances (C1, C2), a word line (WL), and a memory cell (MC1) connected to the bit lines and word line for selection by an address signal, and a restore circuit comprising a coupling/equalizing circuit (12) controlled by a BLR clock and a reference voltage generator (51) for quickly restoring the bit lines. The reference voltage generator (51) comprises both static and dynamic current sources. The static current source consists of a small N MOS transistor (N52) operating as a resistor load, while the dynamic current source consists of at least one small P MOS transistor (P'53, . . . ), connected in parallel with the N MOS transistor, and gated with a clock (BCC', . . . ) derived from the BLR clock, so that the P MOS transistor is turned ON during the restore time. An additional N device (N54) may be inserted between the reference line (RL) and ground (GND). The improved reference voltage of the present invention significantly reduces both consumed silicon area and restore time.

公开(公告)号：US5063537A

公开(公告)日：1991-11-05

申请号：US414339

申请日：1989-09-29

申请人： Chekib Akrout ,  Pierre Coppens ,  Yves Gautier ,  Pierre-Yves Urena

发明人： Chekib Akrout ,  Pierre Coppens ,  Yves Gautier ,  Pierre-Yves Urena

IPC分类号： G11C15/04 ,  H03K19/177

CPC分类号： G11C15/04 ,  H03K19/17712

摘要： A reprogrammable logic fuse (RLF) based on a 6 device standard Static Random Access Memory (SRAM) cell includes a storage element comprised of four cross coupled FETs. A fifth FET is mounted in a transmission gate configuration between the bit line and a first common node of the storage element. Its gate electrode is connected to the word line. This FET is used to write the appropriate control data in the storage element for bit personality store. A sixth FET is also mounted in a transmission gate configuration between the second common node of the storage element and an output line. Its gate electrode is connected to the input line. This sixth FET ensures that a logical function, e.g. AND/NAND is achieved between the signals available at the second common node and on the input line. Other configurations of said sixth FET are allowed. These reprogrammable logic fuses may be disposed in matrixes to constitute reloadable logic arrays and Reloadable PLAs (RPLAs). In the latter case, in the AND array the input and output lines are respectively the product term lines (if bit partitioning is employed) and AND term lines (or Match Lines). In the OR array, the input and output lines are respectively the Match Out lines (the signal on the Match Line after complementation) and the OR out lines. RPLAs employing these RLF's can be dynamically reprogrammed to allow in system logical reconfiguration in real time.

公开(公告)号：US5023841A

公开(公告)日：1991-06-11

申请号：US313216

申请日：1989-02-21

申请人： Chekib Akrout ,  Pierre Coppens ,  Bernard Denis ,  Pierre-Yves Urena

发明人： Chekib Akrout ,  Pierre Coppens ,  Bernard Denis ,  Pierre-Yves Urena

IPC分类号： G11C11/419 ,  G11C7/06 ,  G11C8/16

CPC分类号： G11C8/16 ,  G11C7/065

摘要： In combination with an electronic memory of the type having a plurality of memory cells (CA, . . . CN) connected between two bit lines (BLT, BLC) having inherent bit line capacitances (C1, C2), there is disclosed an improved sense amplifier (15) comprised of two stages. A first stage (16) includes a first clocked latch (5) having an enable device (T5), gated by a first control signal (SSA) and bit switches (T6, T7) connected between the common nodes (6, 7) of said first clocked latch and said bit lines, and gated by a bit switch control signal (BS) to provide an output signal on first data lines (DLT, DLC). A second stage (17) includes a second clocked latch (20) having an enable device (T24) gated by a second signal (SL) and data switches (T28, T29) connected between second data lines (DT, DC) at the same potential as data output nodes (21, 22) of said second clocked latch and said first data lines (DLT, DLC). Said data switches (T28, T29) are gated by a data switch control signal (DS) which is derived from the bit switch control signal (BS), so that the first and second stages (16, 17) operate sequentially to amplify the data continuously along the sensing chain of the data path during a READ operation to provide a data output signal on said data output nodes. The data is then available for further processing at the output terminal (24) of the output driver (23).

摘要翻译： 结合具有连接在具有固有位线电容（C1，C2）的两个位线（BLT，BLC）之间的多个存储单元（CA，...）的类型的电子存储器，公开了一种改进的感测 放大器（15）由两个阶段组成。 第一级（16）包括具有使能装置（T5）的第一时钟锁存器（5），由第一控制信号（SSA）和连接在公共节点（6,7）之间的位开关（T6，T7） 所述第一时钟锁存器和所述位线，并且由位开关控制信号（BS）选通以在第一数据线（DLT，DLC）上提供输出信号。 第二级（17）包括第二时钟锁存器（20），其具有由第二信号（SL）选通的使能装置（T24）和连接在相同的第二数据线（DT，DC）之间的数据开关（T28，T29） 作为所述第二时钟锁存器和所述第一数据线（DLT，DLC）的数据输出节点（21,22）的电位。 所述数据开关（T28，T29）由从比特开关控制信号（BS）导出的数据切换控制信号（DS）选通，使得第一和第二级（16,17）依次操作以放大数据 在读取操作期间沿着数据路径的感测链连续地提供在所述数据输出节点上的数据输出信号。 然后，该数据可用于在输出驱动器（23）的输出端（24）处进一步处理。