公开(公告)号：US20070086262A1

公开(公告)日：2007-04-19

申请号：US11550081

申请日：2006-10-17

Applicant: Chetan Verma ,  Rohit Gupta ,  Piyush Mishra

Inventor： Chetan Verma ,  Rohit Gupta ,  Piyush Mishra

IPC: G11C8/00

CPC classification number: H01L27/0207 ,  H01L27/11898

Abstract: A semiconductor integrated circuit (IC) chip includes at least one core logic module located in a central area of the chip and having a core input/output (I/O) and a plurality of I/O pads disposed on a periphery of the chip. Narrow logic blocks including buffers and delay elements separate the core logic module from the I/O pads. The core I/O is coupled to the I/O pads by way of the buffers and delay elements of the narrow logic blocks.

Abstract translation: 半导体集成电路（IC）芯片包括位于芯片的中心区域中的至少一个核心逻辑模块，并具有核心输入/输出（I / O）和设置在芯片外围的多个I / O焊盘 。 包括缓冲器和延迟元件的窄逻辑块将核心逻辑模块与I / O焊盘分开。 核心I / O通过窄逻辑块的缓冲器和延迟元件耦合到I / O焊盘。