公开(公告)号：US20060184804A1

公开(公告)日：2006-08-17

申请号：US11057373

申请日：2005-02-15

申请人： Rahoul Varma ,  Marc Wicks ,  Gareth Duncan ,  David McHale ,  Mike Livesley

发明人： Rahoul Varma ,  Marc Wicks ,  Gareth Duncan ,  David McHale ,  Mike Livesley

IPC分类号： G06F12/14

CPC分类号： G06F12/1425 ,  G06F12/0897

摘要： A data processing apparatus operable to access data values, each data value being associated with a respective address value is disclosed. The data processing apparatus comprises: a processor operable to process an instruction which causes a data access request; a main memory operable to store data values, said main memory having a region of secure data values; a cache operable to store previously accessed data values; and cache interface logic comprising: data transaction logic operable to receive a data access request from said processor requesting a data value be accessed in said cache, said data access request having an address value and a security attribute associated therewith; and security determination logic operable, in the event that said security attribute indicates a non-secure data access request, to determine whether said non-secure data access request is associated with said region of secure data values by interrogating a data region allocation table and, in the event that said data region allocation table provides an indication that said address value is not associated with said secure data region, to enable said data access request to complete. By determining whether the non-secure data access request is not associated with the region of secure data, it is possible to ensure that no non-secure data accesses occur for address values within a secure region.

摘要翻译： 公开了一种用于访问数据值的数据处理装置，每个数据值与相应的地址值相关联。 数据处理装置包括：处理器，可操作以处理引起数据访问请求的指令; 主存储器，用于存储数据值，所述主存储器具有安全数据值的区域; 用于存储先前访问的数据值的缓存; 以及高速缓存接口逻辑，包括：数据事务逻辑，可操作以从所述处理器接收请求在所述高速缓存中访问的数据值的数据访问请求，所述数据访问请求具有与之相关联的地址值和安全属性; 以及安全性确定逻辑，用于在所述安全属性指示非安全数据访问请求的情况下，通过询问数据区域分配表来确定所述非安全数据访问请求是否与所述安全数据值区域相关联， 在所述数据区域分配表提供所述地址值未与所述安全数据区域相关联的指示的情况下，使所述数据访问请求完成。 通过确定非安全数据访问请求是否与安全数据的区域相关联，可以确保对安全区域内的地址值不发生非安全数据访问。

公开(公告)号：US20060288170A1

公开(公告)日：2006-12-21

申请号：US11155871

申请日：2005-06-20

申请人： Rahoul Varma ,  David McHale ,  Philippe Raphalen ,  Christophe Evrard ,  Cedric Airaud

发明人： Rahoul Varma ,  David McHale ,  Philippe Raphalen ,  Christophe Evrard ,  Cedric Airaud

IPC分类号： G06F12/00

CPC分类号： G06F12/0888

摘要： A data processing apparatus and a method for caching data values in data processing apparatus comprising a level one cache and a level two cache is disclosed. Both the level one cache and the level two cache are operable to store the data values. The method comprises the steps of: a) receiving a transaction request in which a data transaction relating to a data value is requested to occur, the transaction request including cache policy attributes associated with an address of the data value; and b) determining from the cache policy attributes whether or not the data value can be stored by the level one cache and the level two cache and, if so, in which one of the level one cache and the level two cache the data value is to be stored in order to ensure that the data value is prevented from being stored in both the level one cache and the level two cache. Providing cache policy attributes with each data transaction enables a simple determination to be made of which cache should be used to store each data value, with other caches being prevented from storing that data value. Such an approach obviates the need to perform any complex operations in order to determine which cache should be used to store that data value. Hence, a data value may be prevented from being stored in both the level one cache and the level two cache at any one time which ensures that the level one cache and level two cache do not store duplicate data thereby increasing the likelihood of a cache hit within level one or level two for any data value.

摘要翻译： 公开了一种用于在包括一级缓存和二级高速缓存的数据处理装置中缓存数据值的数据处理装置和方法。 一级缓存和两级高速缓存均可操作以存储数据值。 该方法包括以下步骤：a）接收请求发生与数据值相关的数据事务的事务请求，所述事务请求包括与所述数据值的地址相关联的高速缓存策略属性; 以及b）从所述高速缓存策略属性确定所述一级缓​​存和所述二级高速缓存是否可以存储所述数据值，并且如果是，则在所述一级缓​​存和所述二级缓存中的哪一级缓存中所述数据值为 以便确保数据值被防止存储在一级缓存和二级高速缓存中。 为每个数据事务提供高速缓存策略属性使得能够简单地确定应该使用哪个缓存来存储每个数据值，防止其他高速缓存存储该数据值。 这种方法避免了执行任何复杂操作以确定应该使用哪个缓存来存储该数据值的需要。 因此，可以防止数据值在任何一个时间被存储在一级缓存和二级高速缓存中，这确保一级缓存和二级高速缓存不存储重复数据，从而增加高速缓存命中的可能性 在一级或二级任意数据值。

公开(公告)号：US20060112310A1

公开(公告)日：2006-05-25

申请号：US10981741

申请日：2004-11-05

申请人： David McHale ,  Rahoul Varma ,  Marc Wicks ,  Mike Livesley ,  Gareth Duncan

发明人： David McHale ,  Rahoul Varma ,  Marc Wicks ,  Mike Livesley ,  Gareth Duncan

IPC分类号： G06F11/00

CPC分类号： G06F11/348

摘要： The present invention provides a data processing apparatus and method for storing trace data. The data processing apparatus comprises a bus operable to interconnect a number of master devices and slave devices to enable transactions to be routed between the master and slave devices. Each master device is able to initiate a transaction, with the transaction specifying a transaction address. A cache is interposed between at least one of the master devices and the bus and is operable to receive the transaction issued by that master device. The cache has a cache memory and a cache controller operable to control access to the cache memory. The cache controller comprises caching logic operable to selectively cache a data value of the transaction at a location in the cache memory chosen dependent on the transaction address. Control storage is provided identifying a trace address range specifying a trace region. Further, trace logic is provided which is operable to selectively generate as trace data one or more attributes associated with the transaction and to provide in association with that trace data a trace address selected from the trace address range. The caching logic is then operable to store the trace data at a location in the cache memory chosen dependent on the trace address. In this way, the cache can be used in a flexible manner to not only act as a normal cache but also to selectively store within the cache trace data.

摘要翻译： 本发明提供一种用于存储跟踪数据的数据处理装置和方法。 数据处理装置包括总线，其可操作以互连多个主设备和从设备，以使事务能够在主设备和从设备之间路由。 每个主设备能够启动事务，事务指定事务地址。 高速缓存插在至少一个主设备和总线之间，并且可操作以接收该主设备发出的交易。 高速缓存具有缓存存储器和高速缓存控制器，其可操作以控制对高速缓冲存储器的访问。 高速缓存控制器包括缓存逻辑，其可操作以选择性地高速缓存在取决于交易地址选择的高速缓冲存储器中的位置处的事务的数据值。 提供控制存储器，标识指定跟踪区域的跟踪地址范围。 此外，提供跟踪逻辑，其可操作以选择性地生成作为跟踪数据的与事务相关联的一个或多个属性，并且与跟踪数据相关联地提供从跟踪地址范围中选择的跟踪地址。 然后，缓存逻辑可操作以将跟踪数据存储在根据跟踪地址选择的高速缓冲存储器中的位置。 以这种方式，可以以灵活的方式使用高速缓存，以便不仅用作正常高速缓存，而且可以选择性地存储在高速缓存跟踪数据内。