公开(公告)号：US07260792B2

公开(公告)日：2007-08-21

申请号：US11126497

申请日：2005-05-10

申请人： Chandrashekar L. Chetput ,  Ramesh S. Mayiladuthurai ,  Prasenjit Biswas

发明人： Chandrashekar L. Chetput ,  Ramesh S. Mayiladuthurai ,  Prasenjit Biswas

IPC分类号： G06F17/50

CPC分类号： G06F17/5063 ,  G06F17/505 ,  G06F2217/86

摘要： A method for modeling a mixed-language and mixed-signal (MLMS) design is disclosed. The method includes receiving an MLMS design comprising at least a digital driver, a digital receiver, and an analog block connected by an MLMS net in a hierarchical structure and identifying analog-digital boundaries of the MLMS design. For each analog-digital boundary, the method further includes a) selecting a connect module (CM) by using a predetermined discipline resolution procedure; b) determining input driving values of the CM; and c) connecting the digital driver, the digital receiver, and the analog block to the CM. The method repeats steps a), b), and c) on all analog-digital boundaries of the MLMS design.

摘要翻译： 公开了一种混合语言和混合信号（MLMS）设计建模方法。 该方法包括接收MLMS设计，该MLMS设计至少包括数字驱动器，数字接收器以及由分层结构中的MLMS网连接的模拟块，并且识别MLMS设计的模拟数字边界。 对于每个模拟数字边界，该方法还包括：a）通过使用预定的纪律解决程序来选择连接模块（CM）; b）确定CM的输入驱动值; 以及c）将数字驱动器，数字接收器和模拟块连接到CM。 该方法在MLMS设计的所有模拟 - 数字边界上重复步骤a），b）和c）。

公开(公告)号：US07251795B2

公开(公告)日：2007-07-31

申请号：US10952222

申请日：2004-09-27

申请人： Prasenjit Biswas ,  Ramesh S. Mayiladuthurai ,  Chandrashekar L. Chetput ,  Abhijeet Kolpekwar

发明人： Prasenjit Biswas ,  Ramesh S. Mayiladuthurai ,  Chandrashekar L. Chetput ,  Abhijeet Kolpekwar

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A method for connecting Verilog-AMS and VHDL-AMS components in a mixed-language mixed-signal design includes receiving a mixed-language mixed-signal design, where the mixed-language mixed-signal design comprises one or more VHDL-AMS and Verilog-AMS components, including a first VHDL-AMS component and a first Verilog-AMS component. The method further includes receiving a predetermined set of connection rules, resolving incompatibilities between the first VHDL-AMS component and the first Verilog-AMS component in accordance with the predetermined set of connection rules, and connecting the first VHDL-AMS component to the first Verilog-AMS component.

摘要翻译： 在混合语言混合信号设计中连接Verilog-AMS和VHDL-AMS组件的方法包括接收混合语言混合信号设计，其中混合语言混合信号设计包括一个或多个VHDL-AMS和Verilog -AMS组件，包括第一个VHDL-AMS组件和第一个Verilog-AMS组件。 该方法还包括接收一组预定的连接规则，根据预定的连接规则集解决第一VHDL-AMS组件与第一Verilog-AMS组件之间的不兼容性，并将第一VHDL-AMS组件连接到第一个Verilog -AMS组件。