公开(公告)号：US06737904B1

公开(公告)日：2004-05-18

申请号：US09439970

申请日：1999-11-12

申请人： Remi Butaud ,  Bernard Ginetti

发明人： Remi Butaud ,  Bernard Ginetti

IPC分类号： H03K300

CPC分类号： G06F1/04 ,  H04B15/06 ,  H04B2215/067

摘要： A method of producing a clock signal with reduced electromagnetic interference spectral components includes providing a first clock signal; producing a second clock signal by delaying the first clock signal; and generating a jittered clock signal by switching between the first clock signal and the second clock signal at times selected responsive to a random number generator. A GSM phone comprises a clock configured to produce a first clock signal; a delay element coupled to the clock to produce a second clock signal by delaying the first clock signal; a multiplexer coupled to the clock and to the delay element to select between the clock and the delay element; a random number generator coupled to the multiplexer wherein the multiplexer generates a jittered clock signal by switching between the first clock signal and the second clock signal responsive to the random number generator; and a plurality of GSM phone components respectively coupled to the multiplexer to use the jittered clock signal as an input clock for the component.

摘要翻译： 一种产生具有降低的电磁干扰频谱分量的时钟信号的方法包括：提供第一时钟信号; 通过延迟第一时钟信号产生第二时钟信号; 以及通过在响应于随机数发生器选择的时间在第一时钟信号和第二时钟信号之间切换来产生抖动的时钟信号。 GSM电话包括被配置为产生第一时钟信号的时钟; 延迟元件，其耦合到所述时钟，以通过延迟所述第一时钟信号产生第二时钟信号; 耦合到时钟和延迟元件的多路复用器，用于在时钟和延迟元件之间进行选择; 耦合到所述多路复用器的随机数发生器，其中所述多路复用器通过响应于所述随机数发生器在所述第一时钟信号和所述第二时钟信号之间切换来产生抖动时钟信号; 以及分别耦合到多路复用器的多个GSM电话组件，以将抖动的时钟信号用作该组件的输入时钟。

公开(公告)号：US06034881A

公开(公告)日：2000-03-07

申请号：US60113

申请日：1998-04-15

申请人： Remi Butaud

发明人： Remi Butaud

IPC分类号： G11C17/12 ,  G11C7/00

CPC分类号： G11C17/12

摘要： The present invention, generally speaking, provides compact ROM layouts for trace or via-programmable (e.g., metal programmable) using transistor stacks. A number of field effect transistors (for example, eight) are coupled in series. For a particular transistor, a logic zero is programmed by forming a metal trace between the source and drain of the transistor. To read out the value of a particular bit, a logic zero is applied to the gate of the corresponding transistor. Logic ones are applied to the gates of the remaining transistors in the stack. A logic one precharge signal is applied to the top and bottom of the stack. A logic zero is then applied to the bottom of the stack. The logic zero reaches a sense amplifier coupled to the top of the transistor stack only if there is a short circuit across the transistor being read, indicating a logic zero bit value. Otherwise, the precharged logic one condition remains. Transistor stacks may be paired in a similar manner as individual transistors in conventional layouts. A very efficient ROM layout results.

摘要翻译： 一般而言，本发明通过使用晶体管堆栈提供用于跟踪或经过可编程（例如，金属可编程）的紧凑的ROM布局。 多个场效应晶体管（例如8个）串联耦合。 对于特定晶体管，通过在晶体管的源极和漏极之间形成金属迹线来编程逻辑零。 为了读出特定位的值，逻辑零被施加到相应晶体管的栅极。 逻辑电路被施加到堆叠中的剩余晶体管的栅极。 逻辑一个预充电信号被施加到堆叠的顶部和底部。 然后将逻辑零应用于堆栈的底部。 只有当正在读取晶体管的短路时，逻辑0到达耦合到晶体管堆栈顶部的读出放大器，表示逻辑零位值。 否则，预充电逻辑一个条件仍然存在。 晶体管堆叠可以以与传统布局中的单个晶体管类似的方式配对。 一个非常高效的ROM布局结果。