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1.发明申请公开(公告)号：US20100274990A1
公开(公告)日：2010-10-28
申请号：US12585573
申请日：2009-09-17
CPC分类号： G06F9/3001 , G06F9/30036 , G06F9/30065 , G06F9/3893
摘要： An apparatus and method for performing SIMD multiply-accumulate operations includes SIMD data processing circuitry responsive to control signals to perform data processing operations in parallel on multiple data elements. Instruction decoder circuitry is coupled to the SIMD data processing circuitry and is responsive to program instructions to generate the required control signals. The instruction decoder circuitry is responsive to a single instruction (referred to herein as a repeating multiply-accumulate instruction) having as input operands a first vector of input data elements, a second vector of coefficient data elements, and a scalar value indicative of a plurality of iterations required, to generate control signals to control the SIMD processing circuitry. In response to those control signals, the SIMD data processing circuitry performs the plurality of iterations of a multiply-accumulate process, each iteration involving performance of N multiply-accumulate operations in parallel in order to produce N multiply-accumulate data elements. For each iteration, the SIMD data processing circuitry determines N input data elements from said first vector and a single coefficient data element from the second vector to be multiplied with each of the N input data elements. The N multiply-accumulate data elements produced in a final iteration of the multiply-accumulate process are then used to produce N multiply-accumulate results. This mechanism provides a particularly energy efficient mechanism for performing SIMD multiply-accumulate operations, as for example are required for FIR filter processes.
摘要翻译： 用于执行SIMD乘法累加操作的装置和方法包括响应于控制信号的SIMD数据处理电路，以对多个数据元素并行地执行数据处理操作。 指令解码器电路耦合到SIMD数据处理电路，并且响应于程序指令以产生所需的控制信号。 指令解码器电路响应于具有作为输入操作数的输入数据元素的第一向量，系数数据元素的第二向量和指示多个的标量值的单个指令（这里称为重复乘法累加指令） 以产生控制信号以控制SIMD处理电路。 响应于这些控制信号，SIMD数据处理电路执行多次累积处理的多次迭代，每次迭代涉及并行执行N次乘法运算，以产生N个乘法累加数据元素。 对于每次迭代，SIMD数据处理电路从所述第一向量确定N个输入数据元素，并且从第二向量确定要与N个输入数据元素中的每一个相乘的单个系数数据元素。 然后，在乘法累加过程的最终迭代中产生的N个乘法累加数据元素用于产生N个乘法累加结果。 该机制提供了用于执行SIMD乘法累加操作的特别高效的机制，例如FIR滤波器处理所需要的。
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2.发明授权公开(公告)号：US08443170B2
公开(公告)日：2013-05-14
申请号：US12585573
申请日：2009-09-17
CPC分类号： G06F9/3001 , G06F9/30036 , G06F9/30065 , G06F9/3893
摘要： An apparatus and method for performing SIMD multiply-accumulate operations includes SIMD data processing circuitry responsive to control signals to perform data processing operations in parallel on multiple data elements. Instruction decoder circuitry is coupled to the SIMD data processing circuitry and is responsive to program instructions to generate the required control signals. The instruction decoder circuitry is responsive to a single instruction (referred to herein as a repeating multiply-accumulate instruction) having as input operands a first vector of input data elements, a second vector of coefficient data elements, and a scalar value indicative of a plurality of iterations required, to generate control signals to control the SIMD processing circuitry. In response to those control signals, the SIMD data processing circuitry performs the plurality of iterations of a multiply-accumulate process, each iteration involving performance of N multiply-accumulate operations in parallel in order to produce N multiply-accumulate data elements. For each iteration, the SIMD data processing circuitry determines N input data elements from said first vector and a single coefficient data element from the second vector to be multiplied with each of the N input data elements. The N multiply-accumulate data elements produced in a final iteration of the multiply-accumulate process are then used to produce N multiply-accumulate results. This mechanism provides a particularly energy efficient mechanism for performing SIMD multiply-accumulate operations, as for example are required for FIR filter processes.
摘要翻译： 用于执行SIMD乘法累加操作的装置和方法包括响应于控制信号的SIMD数据处理电路，以对多个数据元素并行地执行数据处理操作。 指令解码器电路耦合到SIMD数据处理电路，并且响应于程序指令以产生所需的控制信号。 指令解码器电路响应于具有作为输入操作数的输入数据元素的第一向量，系数数据元素的第二向量和指示多个的标量值的单个指令（这里称为重复乘法累加指令） 以产生控制信号以控制SIMD处理电路。 响应于这些控制信号，SIMD数据处理电路执行多次累积处理的多次迭代，每次迭代涉及并行执行N次乘法运算，以产生N个乘法累加数据元素。 对于每次迭代，SIMD数据处理电路从所述第一向量确定N个输入数据元素，并且从第二向量确定要与N个输入数据元素中的每一个相乘的单个系数数据元素。 然后，在乘法累加过程的最终迭代中产生的N个乘法累加数据元素用于产生N个乘法累加结果。 该机制提供了用于执行SIMD乘法累加操作的特别高效的机制，例如FIR滤波器处理所需要的。
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