公开(公告)号：US07305639B2

公开(公告)日：2007-12-04

申请号：US11055863

申请日：2005-02-11

申请人： Michael Stephen Floyd ,  Joshua David Friedrich ,  Elspeth Anne Huston ,  Wolfgang Roesner ,  Rick John Weiss

发明人： Michael Stephen Floyd ,  Joshua David Friedrich ,  Elspeth Anne Huston ,  Wolfgang Roesner ,  Rick John Weiss

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F2217/78

摘要： A method, an apparatus and computer instructions are provided for specifying multiple voltage domains of a signal and macros in a processor chip and validating physical implementation and interconnections of the signal and macros. A set of attributes is provided for designs to define multiple voltage domains of a signal and macros in a processor chip. A first validation mechanism is then provided to validate that no electrical or logical errors created by logical connections between macros as defined by the set of attributes. A translation mechanism is provided to translate logical voltage description to a physical netlist for designers to connect powers to macros and signals. A second validation mechanism is provided to validate physical implementation adhere to designers' intent according to the set of attributes defined in the logical design.

摘要翻译： 提供了一种用于指定处理器芯片中的信号和宏的多个电压域并验证信号和宏的物理实现和互连的方法，装置和计算机指令。 提供了一组属性，用于设计以定义处理器芯片中的信号和宏的多个电压域。 然后提供第一验证机制以验证由该属性集所定义的宏之间的逻辑连接所产生的电或逻辑错误。 提供了一种翻译机制，用于将逻辑电压描述转换为物理网表，供设计师将功能连接到宏和信号。 提供了第二个验证机制，以根据逻辑设计中定义的属性集来验证物理实现符合设计者的意图。