公开(公告)号：US12079102B2

公开(公告)日：2024-09-03

申请号：US17376120

申请日：2021-07-14

申请人： Ronghui Gu ,  Jason Nieh ,  Runzhou Tao

发明人： Ronghui Gu ,  Jason Nieh ,  Runzhou Tao

IPC分类号： G06F11/36

CPC分类号： G06F11/3604

摘要： Mechanisms for proving the correctness of software on relaxed memory hardware are provided, the mechanisms comprising: receiving a specification, a hardware model, and an implementation for the software to be executed on the relaxed memory hardware; evaluating the software using a sequentially consistent hardware model; evaluating the software using a relaxed memory hardware model and at least one of the following conditions: a data-race-free (DRF)-kernel condition; a no-barrier-misuse condition; a memory-isolation condition; a transactional-page-table condition; a write-once-kernel-mapping condition; and a weak-memory-isolation condition; and outputting an indication of whether the software is correct based on the evaluating the software using the sequentially consistent hardware model and the evaluating the software using the relaxed memory hardware model.

公开(公告)号：US20220019514A1

公开(公告)日：2022-01-20

申请号：US17376120

申请日：2021-07-14

申请人： Ronghui Gu ,  Jason Nieh ,  Runzhou Tao

发明人： Ronghui Gu ,  Jason Nieh ,  Runzhou Tao

IPC分类号： G06F11/36

摘要： Mechanisms for proving the correctness of software on relaxed memory hardware are provided, the mechanisms comprising: receiving a specification, a hardware model, and an implementation for the software to be executed on the relaxed memory hardware; evaluating the software using a sequentially consistent hardware model; evaluating the software using a relaxed memory hardware model and at least one of the following conditions: a data-race-free (DRF)-kernel condition; a no-barrier-misuse condition; a memory-isolation condition; a transactional-page-table condition; a write-once-kernel-mapping condition; and a weak-memory-isolation condition; and outputting an indication of whether the software is correct based on the evaluating the software using the sequentially consistent hardware model and the evaluating the software using the relaxed memory hardware model.

公开(公告)号：US20240012728A1

公开(公告)日：2024-01-11

申请号：US18220229

申请日：2023-07-10

申请人： Jason Nieh ,  Ronghui Gu ,  Xuheng Li ,  Xupeng Li

发明人： Jason Nieh ,  Ronghui Gu ,  Xuheng Li ,  Xupeng Li

IPC分类号： G06F11/28 ,  G06F11/36

CPC分类号： G06F11/28 ,  G06F11/3612 ,  G06F11/3636

摘要： Mechanisms for verifying software on a multi-CPU machine are provided, the mechanisms including: using a hardware processor: reordering, in a shared log, a first local CPU event from a local CPU operating on a shared object to be before at least one first prior oracle query corresponding to a prior event from another CPU based on whether the first local CPU event can be reordered with respect to the prior event without changing the multi-CPU machine's behavior with respect to the shared object; merging first consecutive oracle queries including the at least one first prior oracle query in the shared log; and verifying the software based on the merged first consecutive oracle queries.