摘要:
A transponder having a dynamic remapping circuit remaps a value of decision threshold voltage Vdtc and a value of optical power RXP to a reference voltage Vref to minimize the bit error rate BER of a communication system. The dynamic remapping circuit implements a bilinear mapping of Vdtc and RXP to Vref with three bilinear remapping constants “a”, “b”, and “c” selected to align a remapped value of Vdtc_opt to a selected Vdtc normalization value, Vdtc_norm. A transponder in accord with an embodiment of the invention prevents BER from exceeding a threshold value of BER whether RXP or OSNR, or both, remain constant, change continuously, or change intermittently. Constants “a”, “b”, and “c” are related to parameters resulting from mathematically fitting a line to data comprising Vdtc_opt versus RXP. Another embodiment comprises a method for dynamically optimizing Vdtc and RXP to Vref in a transponder with a bilinear remapping circuit.
摘要:
A transponder having a dynamic remapping circuit remaps a value of decision threshold voltage Vdtc and a value of optical power RXP to a reference voltage Vref to minimize the bit error rate BER of a communication system. The dynamic remapping circuit implements a bilinear mapping of Vdtc and RXP to Vref with three bilinear remapping constants “a”, “b”, and “c” selected to align a remapped value of Vdtc_opt to a selected Vdtc normalization value, Vdtc_norm. A transponder in accord with an embodiment of the invention prevents BER from exceeding a threshold value of BER whether RXP or OSNR, or both, remain constant, change continuously, or change intermittently. Constants “a”, “b”, and “c” are related to parameters resulting from mathematically fitting a line to data comprising Vdtc_opt versus RXP. Another embodiment comprises a method for dynamically optimizing Vdtc and RXP to Vref in a transponder with a bilinear remapping circuit.
摘要:
A topology for optical transceiver components comprises an electrical signal interface stage, a data timing and signal reformatting stage, and an optical fiber interface stage. Unlike transceiver components known in the art, functions having signals with the most jitter are partitioned into the electrical signal interface stage. Data timing functions, for example retiming or clock and data recovery, are included in the data timing and reformatting stage. Output jitter from the data timing and signal reformatting stage is approximately equal to jitter in a clock signal, enabling use of semiconductor components having jitter greater than SONET limits and thereby increasing a value of production yield. Embodiments of the invention are well suited for 40 G transmitters and receivers in nonconnectorized surface mount packages. 40 G transceivers built in accord with the invention are expected to have lower cost, smaller size, and higher production yield than 40 G transceivers known in the art.
摘要:
A topology for optical transceiver components comprises an electrical signal interface stage, a data timing and signal reformatting stage, and an optical fiber interface stage. Unlike transceiver components known in the art, functions having signals with the most jitter are partitioned into the electrical signal interface stage. Data timing functions, for example retiming or clock and data recovery, are included in the data timing and reformatting stage. Output jitter from the data timing and signal reformatting stage is approximately equal to jitter in a clock signal, enabling use of semiconductor components having jitter greater than SONET limits and thereby increasing a value of production yield. Embodiments of the invention are well suited for 40 G transmitters and receivers in nonconnectorized surface mount packages. 40 G transceivers built in accord with the invention are expected to have lower cost, smaller size, and higher production yield than 40G transceivers known in the art.
摘要:
A transponder having a dynamic remapping circuit remaps a value of decision threshold voltage Vdtc and a value of optical power RXP to a reference voltage Vref to minimize the bit error rate BER of a communication system. The dynamic remapping circuit implements a bilinear mapping of Vdtc and RXP to Vref with three bilinear remapping constants “a”, “b”, and “c” selected to align a remapped value of Vdtc_opt to a selected Vdtc normalization value, Vdtc_norm. A transponder in accord with an embodiment of the invention prevents BER from exceeding a threshold value of BER whether RXP or OSNR, or both, remain constant, change continuously, or change intermittently. Constants “a”, “b”, and “c” are related to parameters resulting from mathematically fitting a line to data comprising Vdtc_opt versus RXP. Another embodiment comprises a method for dynamically optimizing Vdtc and RXP to Vref in a transponder with a bilinear remapping circuit.
摘要:
A transponder having a dynamic remapping circuit remaps a value of decision threshold voltage Vdtc and a value of optical power RXP to a reference voltage Vref to minimize the bit error rate BER of a communication system. The dynamic remapping circuit implements a bilinear mapping of Vdtc and RXP to Vref with three bilinear remapping constants “a”, “b”, and “c” selected to align a remapped value of Vdtc_opt to a selected Vdtc normalization value, Vdtc_norm. A transponder in accord with an embodiment of the invention prevents BER from exceeding a threshold value of BER whether RXP or OSNR, or both, remain constant, change continuously, or change intermittently. Constants “a”, “b”, and “c” are related to parameters resulting from mathematically fitting a line to data comprising Vdtc_opt versus RXP. Another embodiment comprises a method for dynamically optimizing Vdtc and RXP to Vref in a transponder with a bilinear remapping circuit.