摘要:
A clock modulation circuit modulates the frequency of a clock signal to generate a modulated clock signal. A wait requesting signal receives frequency information indicating the frequency of the modulated clock signal and, when the frequency information indicates a frequency higher than a reference frequency, generates a wait requesting signal to an external bus interface. Since an optimum wait cycle is inserted to the external bus interface according to a change of the frequency of the modulated clock signal, needless wait cycle can be prevented from being inserted to the external bus interface. As a result of this, it is possible to disperse the peak of radiated noise which is caused by the clock signal and to reduce electromagnetic interference, without decreasing performance of a system. Namely, it can serve both market needs for reducing noise and speeding up.
摘要:
A server includes a database that stores, in association with user identification information for identifying the user who purchases or uses goods or services, the number of points that are assigned to the user according to the purchased or used goods or services and that can be used to purchase goods or services. The server divides the points stored in association with the user identification information into user's own points that only the user can use; and other's points that other users other than the user can use, before storing the points in the database.
摘要:
In an integrated circuit having an internal supply voltage generation circuit which generates an internal supply voltage by descending an external supply voltage, there is provided an internal circuit which operates with a supplied internal supply voltage. The internal supply voltage generation circuit changes an internal supply voltage level to be generated in accordance with an operation speed of the internal circuit. Preferably the semiconductor integrated circuit includes a clock control circuit which generates an internal clock signal the frequency of which is controlled in accordance with the operation speed of the internal circuit. When the internal clock signal is controlled to have a higher frequency, the internal supply voltage is controlled to be higher. Also, when the internal clock signal is controlled to have a lower frequency, the internal supply voltage is controlled to be lower.