公开(公告)号：US08711874B2

公开(公告)日：2014-04-29

申请号：US13476294

申请日：2012-05-21

Applicant: Sagar W. Kenkare

Inventor： Sagar W. Kenkare

IPC: H04J3/02

CPC classification number: H04L12/66

Abstract: Embodiments may include two gigabit Ethernet controllers integrated within a single chip and an I/O bridge coupled to the two gigabit Ethernet controllers and integrated within the single chip. The system may further include an I/O function coupled to the I/O bridge that is integrated within the single chip. The I/O function may include I/O logic and an I/O buffer integrated within the single chip and coupled to the I/O bridge and/or the two gigabit Ethernet controllers. A timing function or timing block may also be coupled to the I/O bridge and integrated within the single chip. A host system may be coupled to the I/O bridge. The I/O bridge may further include a primary bus controller, which may be a primary PCI bus controller. The controller or controller block may include control and status registers that may be coupled to the primary bus controller.

Abstract translation: 实施例可以包括集成在单个芯片内的两个千兆位以太网控制器以及耦合到两个千兆以太网控制器并集成在单个芯片内的I / O桥。 该系统还可以包括耦合到集成在单个芯片内的I / O桥的I / O功能。 I / O功能可以包括集成在单个芯片内的I / O逻辑和I / O缓冲器，并且耦合到I / O桥和/或两个千兆以太网控制器。 定时功能或定时块也可以耦合到I / O桥并且集成在单个芯片内。 主机系统可以耦合到I / O桥。 I / O桥可以进一步包括主总线控制器，其可以是主PCI总线控制器。 控制器或控制器块可以包括可以耦合到主总线控制器的控制和状态寄存器。

公开(公告)号：US20120233371A1

公开(公告)日：2012-09-13

申请号：US13476294

申请日：2012-05-21

Applicant: Dr. Sagar W. Kenkare

Inventor： Dr. Sagar W. Kenkare

IPC: G06F13/36

CPC classification number: H04L12/66

Abstract: Embodiments may include two gigabit Ethernet controllers integrated within a single chip and an I/O bridge coupled to the two gigabit Ethernet controllers and integrated within the single chip. The system may further include an I/O function coupled to the I/O bridge that is integrated within the single chip. The I/O function may include I/O logic and an I/O buffer integrated within the single chip and coupled to the I/O bridge and/or the two gigabit Ethernet controllers. A timing function or timing block may also be coupled to the I/O bridge and integrated within the single chip. A host system may be coupled to the I/O bridge. The I/O bridge may further include a primary bus controller, which may be a primary PCI bus controller. The controller or controller block may include control and status registers that may be coupled to the primary bus controller.

Abstract translation: 实施例可以包括集成在单个芯片内的两个千兆位以太网控制器以及耦合到两个千兆以太网控制器并集成在单个芯片内的I / O桥。 该系统还可以包括耦合到集成在单个芯片内的I / O桥的I / O功能。 I / O功能可以包括集成在单个芯片内的I / O逻辑和I / O缓冲器，并且耦合到I / O桥和/或两个千兆以太网控制器。 定时功能或定时块也可以耦合到I / O桥并且集成在单个芯片内。 主机系统可以耦合到I / O桥。 I / O桥可以进一步包括主总线控制器，其可以是主PCI总线控制器。 控制器或控制器块可以包括可以耦合到主总线控制器的控制和状态寄存器。

公开(公告)号：US08249097B2

公开(公告)日：2012-08-21

申请号：US10887067

申请日：2004-07-08

Applicant: Sagar W. Kenkare

Inventor： Sagar W. Kenkare

IPC: H04J3/02

CPC classification number: H04L12/66

Abstract: Aspects of the invention may include two gigabit Ethernet controllers integrated within a single chip and an I/O bridge coupled to the two gigabit Ethernet controllers and integrated within the single chip. The system may further include an I/O function coupled to the I/O bridge that is integrated within the single chip. The I/O function may include I/O logic and an I/O buffer integrated within the single chip and coupled to the I/O bridge and/or the two gigabit Ethernet controllers. A timing function or timing block may also be coupled to the I/O bridge and integrated within the single chip. A host system may be coupled to the I/O bridge. The I/O bridge may further include a primary bus controller, which may be a primary PCI bus controller. The controller or controller block may include control and status registers that may be coupled to the primary bus controller.

Abstract translation: 本发明的方面可以包括集成在单个芯片内的两个千兆以太网控制器以及耦合到两个千兆以太网控制器并且集成在单个芯片内的I / O桥。 该系统还可以包括耦合到集成在单个芯片内的I / O桥的I / O功能。 I / O功能可以包括集成在单个芯片内的I / O逻辑和I / O缓冲器，并且耦合到I / O桥和/或两个千兆以太网控制器。 定时功能或定时块也可以耦合到I / O桥并且集成在单个芯片内。 主机系统可以耦合到I / O桥。 I / O桥可以进一步包括主总线控制器，其可以是主PCI总线控制器。 控制器或控制器块可以包括可以耦合到主总线控制器的控制和状态寄存器。

公开(公告)号：US5611041A

公开(公告)日：1997-03-11

申请号：US359315

申请日：1994-12-19

Applicant: Vlad Bril ,  Alexander Eglit ,  Sagar W. Kenkare

Inventor： Vlad Bril ,  Alexander Eglit ,  Sagar W. Kenkare

IPC: G06F12/00 ,  G06F12/02 ,  G09G5/00 ,  G09G5/14 ,  G09G5/18 ,  G09G5/36 ,  G09G5/39 ,  G09G5/393 ,  G09G5/395 ,  G09G5/40

CPC classification number: G09G5/366 ,  G09G5/395 ,  G09G5/14 ,  G09G5/393 ,  G09G5/40

Abstract: A memory controller, particularly for use in a video controller, is provided which reduces the effect of page misses during memory access. A video port FIFO is provided for buffering data from a video port to a display memory. A CRT FIFO is provided for buffering data from a display memory to a display. If, during a video port FIFO cycle, a page miss is encountered, the video port FIFO cycle is terminated and processing passes to a CRT FIFO CYCLE. If a page miss is encountered during a CRT FIFO cycle, the subsequent video port FIFO cycle will shortened by a number of memory cycles to compensate for the additional memory cycles required by the page miss. Additional data accumulated in the video port FIFO may be transferred to the display memory during a retrace interval. In this manner, memory bandwidth is optimized by removing a non-aligned page miss as the worst case of memory bandwidth utilization.

Abstract translation: 提供了特别用于视频控制器的存储器控​​制器，其减少了存储器访问期间页错误的影响。 视频端口FIFO被提供用于缓冲从视频端口到显示存储器的数据。 提供CRT FIFO用于将数据从显示存储器缓存到显示器。 如果在视频端口FIFO周期期间遇到页面未命中，则视频端口FIFO周期终止，并且处理转到CRT FIFO CYCLE。 如果在CRT FIFO周期期间遇到页错，则后续视频端口FIFO周期将缩短多个存储周期，以补偿页错过所需的额外存储周期。 视频端口FIFO中积累的附加数据可以在回扫间隔期间传送到显示存储器。 以这种方式，通过消除不对齐的页面遗漏作为存储器带宽利用的最坏情况来优化存储器带宽。