公开(公告)号：US07137097B1

公开(公告)日：2006-11-14

申请号：US10877259

申请日：2004-06-25

申请人： Sandeep A. Aji ,  Ankur Narang ,  Shantanu Ganguly

发明人： Sandeep A. Aji ,  Ankur Narang ,  Shantanu Ganguly

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： A method, system, computer system, and computer program product including an algorithm that performs the constraints-based global routing step in the physical design of integrated circuits. The algorithm is based on finding routes for the entire circuit based on constraints being satisfied for the entire design. Initially, for each net, a set of possible routing solutions is determined based on applicable constraints. The possible solutions for the nets are combined to create a highly-connected “intersection graph,” with each intersection graph node representing a net. The intersection graph is partitioned based on constraints and performance criteria. An optimal solution is determined for each partition. The optimal solutions for the partitions are then combined to produce a global routing solution. The global routing solution is provided to a detailed router, which completes the routing for the design.

摘要翻译： 一种方法，系统，计算机系统和计算机程序产品，包括在集成电路的物理设计中执行基于约束的全局路由步骤的算法。 该算法基于基于整个设计满足的约束寻找整个电路的路由。 最初，对于每个网络，基于适用的约束确定一组可能的路由解决方案。 组合网络的可能解决方案以创建高度连接的“交叉图”，每个交叉图节点表示网络。 基于约束和性能标准对交叉图进行分区。 确定每个分区的最优解。 然后组合分区的最佳解决方案以产生全局路由解决方案。 将全局路由解决方案提供给详细的路由器，从而完成设计路由。

公开(公告)号：US6072945A

公开(公告)日：2000-06-06

申请号：US883547

申请日：1997-06-26

申请人： Sandeep A. Aji ,  Manjunath Doreswamy ,  Georgios Konstadinidis

发明人： Sandeep A. Aji ,  Manjunath Doreswamy ,  Georgios Konstadinidis

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  Y10S438/927

摘要： An automated apparatus detects electromigration violations in an integrated circuit design. Starting from the lowest hierarchy of the design so far completed, the parasitic (resistance and capacitance) component values extracted from a layout file are propagated up. Then, at the top-most level, lumping algorithms are employed to calculate the parasitic values for all of the top-most level nets. These values are then passed back down to the lower levels and then at each level, the layout is checked using previously computed parasitic values and EM limits. A peak current, AC-average current and AC-rms current are calculated for every layout, and then compared with the process EM rules for violations, in which the optimum line width and number of vias are specified for each interconnection.

摘要翻译： 一种自动化设备在集成电路设计中检测电路违规。 从设计的最低层次开始到目前为止，从布局文件提取的寄生（电阻和电容）分量值向上传播。 然后，在最高层次，采用统计算法来计算所有最高级网络的寄生值。 然后将这些值传回下一级，然后在每个级别，使用先前计算的寄生值和EM限制检查布局。 针对每个布局计算峰值电流，AC平均电流和AC均方根电流，然后与违反的过程EM规则进行比较，其中为每个互连规定了最佳线宽和通孔数。

公开(公告)号：US5831867A

公开(公告)日：1998-11-03

申请号：US669627

申请日：1996-06-24

申请人： Sandeep A. Aji ,  Meera Kasinathan

发明人： Sandeep A. Aji ,  Meera Kasinathan

IPC分类号： G06F17/50 ,  G06F17/00

CPC分类号： G06F17/5036

摘要： An automated method and system for detecting electromigration violations in signal lines of an integrated circuit design to be fabricated is disclosed. The automated method and system checks conductive traces, vias and/or contacts that are used to route signals to and from various functional cells within the integrated circuit design against predetermined process rules to detect electromigration violations. The operation and effectiveness of the automated method and system are far superior to conventional manual approaches.

摘要翻译： 公开了一种用于检测要制造的集成电路设计的信号线中的电迁移违规的自动化方法和系统。 自动化方法和系统检查导电迹线，通路和/或触点，用于根据预定的工艺规则来检测集成电路设计中的各种功能单元的信号，以检测电迁移违规。 自动化方法和系统的运行和有效性远远优于传统的手动方法。

公开(公告)号：US06480996B1

公开(公告)日：2002-11-12

申请号：US09610746

申请日：2000-07-06

申请人： Sandeep A. Aji ,  Shantanu Ganguly ,  John Paz

发明人： Sandeep A. Aji ,  Shantanu Ganguly ,  John Paz

IPC分类号： G06F1750

CPC分类号： G06F17/5077

摘要： An automatic and parameterized compute implemented method for transposing wires in an integrated circuit design can y bus lines with similar impedances, and therefore similar signal transmission characteristics. Using a specially designed CAD tool, a user can specify a transposing porn, intervals at which to transpose wires, and a metal layer through which to accomplish the transposing in the integrated circuit. Using a routing database the tool then automatically determines the locations in the design where transposing needs to be performed, re-routes the wires being transposed while optimizing the circuit design space being used, and re-routes (or causes the re-route of) any other wires affected by the transposing process. The result is a new version of the routing database reflecting transposition, but with no change to the circuit's netlist.

摘要翻译： 用于在集成电路设计中调换电线的自动和参数化的计算实现方法可以具有类似阻抗的总线线路，因此类似的信号传输特性。 使用专门设计的CAD工具，用户可以指定一个移调的色情片段，用于转置电线的间隔，以及通过该金属层在集成电路中完成转置。 使用路由数据库，工具随后自动确定设计中需要执行转置的位置，重新路由正在转置的电线，同时优化正在使用的电路设计空间，并重新路由（或导致重新路由） 任何其他受转置过程影响的电线。 结果是反映转置的路由数据库的新版本，但没有改变电路的网表。

公开(公告)号：US5963729A

公开(公告)日：1999-10-05

申请号：US882986

申请日：1997-06-26

申请人： Sandeep A. Aji ,  Manjunath Doreswamy ,  Georgios Konstadinidis

发明人： Sandeep A. Aji ,  Manjunath Doreswamy ,  Georgios Konstadinidis

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  Y10S438/927

摘要： An automated method detects electromigration violations in an integrated circuit design. Starting from the lowest hierarchy of the design so far completed, the parasitic (resistance and capacitance) component values extracted from a layout file are propagated up. Then, at the top-most level, lumping algorithms are employed to calculate the parasitic values for all of the top-most level nets. These values are then passed back down to the lower levels and then at each level, the layout is checked using previously computed parasitic values and EM limits. A peak current, AC-average current and AC-rms current are calculated for every layout, and then compared with the process EM rules for violations, in which the optimum line width and number of vias are specified for each interconnection.

摘要翻译： 一种自动化方法可以检测集成电路设计中的电路违规。 从设计的最低层次开始到目前为止，从布局文件提取的寄生（电阻和电容）分量值向上传播。 然后，在最高层次，采用统计算法来计算所有最高级网络的寄生值。 然后将这些值传回下一级，然后在每个级别，使用先前计算的寄生值和EM限制检查布局。 针对每个布局计算峰值电流，AC平均电流和AC均方根电流，然后与违反的过程EM规则进行比较，其中为每个互连规定了最佳线宽和通孔数。