公开(公告)号：US20080253162A1

公开(公告)日：2008-10-16

申请号：US12101266

申请日：2008-04-11

Applicant: Olivier Montfort ,  Sebastien Gaubert ,  Philippe Beliard

Inventor： Olivier Montfort ,  Sebastien Gaubert ,  Philippe Beliard

IPC: G11C17/00 ,  G11C7/00 ,  G11C8/00

CPC classification number: G11C11/5692 ,  G11C17/12 ,  G11C2211/5617

Abstract: The invention concerns a ROM comprising a set of memory points arranged in rows and columns, each memory point capable of storing two bits of data and comprising a single switch controllable to connect together first and second terminals of said switch, each of said first and second terminals being connected to one of first, second and third conductive lines, wherein said switch is connected via said first and second terminals between said first and second lines to encode a first data value, between said first and third lines to encode a second data value, between said second and third lines to encode a third data value, and both of said first and second terminals being connected to the same one of said first, second and third lines to encode a fourth data value.

Abstract translation: 本发明涉及一种ROM，其包括以行和列排列的一组存储器点，每个存储点能够存储两位数据，并且包括可控制以将所述开关的第一和第二端子连接在一起的单个开关，所述第一和第二 端子连接到第一，第二和第三导线之一，其中所述开关经由所述第一和第二端子在所述第一和第二线之间连接，以在所述第一和第三线之间编码第一数据值，以对第二数据值进行编码 ，在所述第二和第三行之间编码第三数据值，并且所述第一和第二终端都被连接到所述第一，第二和第三行中的相同的一个，以对第四数据值进行编码。